USER INTERFACE

COMMANDS

FUNCTION KEYS

REGISTERS


USER INTERFACE

DSP control buttons:

Data or register windows buttons:

Unassemble window display modes:

User defined buttons


START DSP

Start the DSP

It causes the DSP to execute from the instruction at the Program Counter. The status of the DSP (RUN or program counter value) is displayed on the left side of the system status line. Running the DSP when the Automatic Update mode is on (Shift-F6) causes automatic data window refreshing while the DSP is running.

To run the DSP with no interruptions, the update mode must be turned off.

F5 key or the GO command may also be used to start the DSP.


STOP DSP

Stop the DSP

It causes the DSP to stop at the Program Counter. The status of the DSP (RUN or program counter value) is displayed on the left side of the system status line.

Shift-F5 key or the FORCE B may also be used to stop the DSP.


TRACE

STEP

It executes a single DSP instruction with a full screen refresh.

F8 key may also be used to execute one step.

Shift-F8 key combination executes an infinite number of steps.

Shift-F5 key combination or the FORCE B command can be used to stop executing the STEP command.


JUMP

Perform a Jump.    JUMP is similar to STEP, except that a subroutine call is treated as one instruction.  The JUMP command and the pull-down menu can also be used to perform a jump.  The debugger's screen is refreshed after the jump.


RESET

Reset the DSP. The FORCE R command and the pull-down menu can also be used to reset the DSP. The debugger's screen is refreshed after the reset.


GRAPHIC MODE

GRAPH MODE

The graph button is used to display the selected data window graphically.  A graph may be scrolled, scaled, sized, and moved. The Up/Down arrow keys are used to change the  vertical graph scaling.

A graph can have a hexadecimal, decimal, or fractional radix.  One or more data windows can be displayed graphically.  The graph button is placed on the screen only when a data window is selected.  The DISPLAY command may also be used to toggle the graphics mode (on/off).


UPDATE

Toggle the the automatic screen update mode (on/off).  In the automatic screen update mode, and when the DSP is started, the DSP is interrupted periodically to update the data windows and the registers window.  Other resource windows are not updated.

The CONFIG command and the pull-down menu can also be used to toggle the automatic update mode.


FORMAT

Changes the display format (radix) of the selected window.  This button can be used to change the radix of a data window, the registers window, or the command window.  The button is not displayed if other windows are selected.  The radix of the window is displayed on the upper border of the resource window.  The RADIX command can also be used to change the radix of the command window.  Following are the available radices:

Data windows:            Hex, Dec, Fra, Asc, Bin

Graphical Data windows:  Hex, Dec, Fra

Registers window:        Hex, Dec, Fra

Command window:        	 Hex, Dec, Fra, Bin

Flags window             Bin

All other windows:       Hex

The radix of the registers window affects the display of registers X, X0, X1, Y, Y0, Y1, A, B only, All other registers are always displayed and edited in Hex.

The RADIX command may also be used to change the default radix of the command window.


ASS_MODE

ASSEMBLY MODE

Put the unassemble window in the reverse assembly mode.  In the unassemble mode, the DSP's memory is reverse assembled and then placed in the unassemble window.  On-screen editing of the DSP code is permitted in this mode. The reverse assembly mode button is placed on the screen only if the unassemble window is the window selected. The UNASSEMBLE  command may also be used to change the display mode.


SRC_MODE

SOURCE MODE

Put the unassemble window in the source mode.  In the source mode, the DSP code is read from the source text file and then placed in the unassemble window.   On-screen editing of the DSP program is not permitted in the source mode.  The source mode button is placed on the screen only when the unassemble window is selected.  If the source line information is not found by the debugger this button is not displayed.  The UNASSEMBLE  command may also be used to change the display mode.


MIX_MODE

MIXED MODE

Put the unassemble window in the mixed mode.  In the mixed mode, reverse assembly and source instructions are interlaced in the same unassemble window. On-screen editing of the DSP program is not permitted in the mixed mode.  The mixed mode button is displayed on the screen only when an unassemble window is selected.  If the source line information is not found by the debugger this button is not displayed.  The UNASSEMBLE  command may also be used to change the display mode.


User buttons
User defined buttons

A user button is a special case of the ALIAS command.

To create a user button, create an alias but place a '!'(an exclamation sign) as the first character of the alias.  This will create a button next to the last one in the Quick Menu bar with the same name as the alias without the leading '!'.  This name will be shortened to 4 characters for normal size buttons and to 1 character for small buttons.  When this button is pressed, it will activate the alias that created it.

Remember, when you are editting user buttons to use the complete name with the '!' .

Example

ALIAS !man "force b " creates button :

which can be used to execute FORCE B command


COMMANDS

Commands are entered from the command window at the command line prompt .

The last line of the screen displays command sensitive help.

Pressing the space bar displays all the commands available.

Commands List

Entry Rules

Command Help Rules

Command Editor

Macro Command

User defined buttons


COMMANDS-LIST

List of all commands (available by pressing the space bar repeatedly)

ALIAS          Define custom command string

ASSEMBLE       On screen or inline assembler

ASS            On screen or inline assembler

ASM            same as ASSEMBLE

BREAK          Enable, disable display breakpoints

CFORCE         Reset the emulator hardware unit

CHANGE         Change register or memory value

CONFIG         System Configuration Option

COPY           Copy a memory block

DISPLAY        Display memory

DISASSEMBLE    Disassemble memory

EMI            Define EMI parameters(for 56004,56007 etc.)

EVALUATE       Evaluate Expression

FORCE          Reset or stop DSP

GO             Execute DSP program

HELP           Display help screen

INPUT          Assign input file

JUMP           Jump over a subroutine call

LOAD           Load DSP program

LOG            Log all Commands to the Log file

MAP            Memory mapping control

OUTPUT         Assign output file

PATH           Define path directory path

QUIT           Quit LINK program

RADIX          Change default input number base

REFRESH        Disables or enables windows refresh flag

RETURN         Execute code until RETURN opcode is reached

SAVE           Saves memory blocks to file or state

STEP           Single step DSP program

SYMBOL         Display symbol table

TIME           Display execution time

TRACE          Trace through DSP program

UNALIAS        Remove custom command string

UNASSEMBLE     Unassemble memory

UNTIL          Execute DSP program

USE            Use different directory

VARIABLE       Define a New Variable

VERSION        Display revision of LINK's firmware

VIEW           Open text file for viewing

WAIT           Wait specified time

WATCH          Select variable to watch

?              Evaluate Expression


ALIAS
ALIAS [name|key [,"command string"]]

The ALIAS command is used to define a command string representing one or more debugger commands as a single "alias" name. If a name is preceded with an exclamation character(!) it also defines user button.

Multiple commands should be separated by semicolons and entire string needs to be enclosed in quotation marks.  Command parameters are identified by a percent sign followed by a number (%1, %2, ...).  Command string can have assigned a name or one of the function keys.  Supported function keys are as follows:

F1..F12	Function keys 1 to 12

SF1..SF12	Shift and function key combination

AF1..AF12	Alt and function key combination

CF1..CF12	Ctrl and function key combination

The ALIAS command without any parameters will display list of all defined aliases.  If only name/key is specified, the current definition of an alias will be shown.

To remove alias definition use UNALIAS command

Example 1

ALIAS prgload "FORCE R; LOAD %1; GO"

Define "PRGLOAD" alias with one parameter for LOAD

command

Example 2

ALIAS AF2

Display definition for Alt-F2 key combination

Example 3

ALIAS !prgload "FORCE R; LOAD %1; GO"

Define "PRGLOAD" alias and user button with prgl name on it.


ASSEMBLE
ASSEMBLE [address] [mnemonic]

The ASSEMBLE command assembles one DSP instruction.

The optional [address] may be program memory, data memory or a label.  If it is a label LINK determines if it is data or program memory.  If [address] is not specified, the current program counter value will be used.

If the optional [mnemonic] is entered on the command line, the instruction is updated automatically. If [mnemonic] is not entered, the Unassemble window is selected and the cursor is placed at the instruction to assemble.

Example 1

A

Assemble at the address equal to the program counter

Example 2

A START_PROGRAM

Assemble at address labeled START_PROGRAM

Example 3

A P:$100

Assemble at program memory address 100 hex

Example 4

A X:$100

Assemble at data memory address 100 hex

Example 5

A X:$100 ADD A,B

Assemble the instruction "ADD A,B" and place code in memory location X:$100.

Example 6

A ADD A,B

Assemble the instruction "ADD A,B" and place code in  memory location at the Program Counter.


BREAK
BREAK  [breakpoint_number] [OFF] [break_access][break_type] [break_address] [break_block]] [break_count][S][T(expression)]

Enable or Disable Breakpoint (F9)

The BREAK command sets, removes, and displays breakpoints. There are two types of breakpoints: hardware and software breakpoints.

.

BREAK with no arguments displays all breakpoints set.

[breakpoint_number] is a number between 1 and 128 for software breakpoints and 0 for the hardware breakpoint. If this number is omitted for software breakpoints, a default value that starts with one is used and is incremented automatically. If this number is omitted for hardware breakpoints, the default is always zero.

[OFF] is used to remove one breakpoint or all breakpoints.  If a breakpoint number is not entered, all hardware and software breakpoints are removed.

[Break_access] is used to set a hardware breakpoint on memory read(r), write(w), or access(rw). Break_access does not apply to software breakpoints.

[break_type] Determines the breakpoint type. Different break_types apply to hardware and software breakpoints.

[break_count] specifies the number of times the condition must be satisfied before a hardware breakpoint is reached. The break_count does not apply for software breakpoints.  The number may be any number greater than 0 and less than $1000000 (it is a 24 bit counter).  If the count is not specified, it

defaults to one.

[break_address] is the address of the Break. It may be may be program memory, data memory or a symbol. If it is a symbol, LINK determines automatically if it refers to data or program memory.

[break_block] specifies address range. Break_block can be used with hardware breakpoint only. The address range may be program memory, data memory or a symbol. If it is a symbol, LINK determines automatically if it refers to data or program memory

[S] shows options is used to refresh the windows and continue execution.

[T(expression)] allows to stop execution at the breakpoint only if a condition is satisfied. The format of expression is as follows:  T(val1?val2)

Value 1 and 2 can be one of following:

- immediate value (number preceded by "#")

- register

- memory location (SYMBOL or address: P|X|Y:xxxx)

Note: For DSP156 & 166 only P & X memory addressing are available.

Tests supported (?):

     >, >=, <, <=, ==, !=.

Spaces within test syntax are not permitted.

Other Breakpoint Rules:

1. The default breakpoint is a software breakpoint.

2. One hardware breakpoint may be set.

3. There may be up to 128 software breakpoints set simultaneously.

4. If the Unassemble window is selected, function key F9 toggles an unconditional software breakpoint On and Off.

Example 1

BREAK

Display all currently set breakpoints (hardware as well as software).

Example 2

BREAK OFF

Remove all breakpoints

Example 3

BREAK OFF 2

Remove breakpoint number 2

Example 3

BREAK P:$100

Set a software breakpoint at program memory 100 hex

Example 4

BREAK START_PROGRAM

Set a software breakpoint on program memory instruction labeled START_PROGRAM

Example 5

BREAK pcf P:LABEL_1#$20

Brek on program memory fetch and execution of the instruction at range of instructions between P:LABEL_1 and    P:LABEL_1+32 (hardware breakpoint)

Example 6

BREAK pcf P:LABEL_1 7

Break on the 7th program memory fetch and execution of the instruction at P:LABEL_1 (hardware breakpoint).

Example 7

BREAK pcm r P:LABEL_1

Break when program memory location P:LABEL_1 is read once (hardware breakpoint).

Example 8

BREAK pcm r P:LABEL_1 7

Break when program memory location P:LABEL_1 read 7 times (hardware breakpoint).

Example 9

BREAK pcm w P:LABEL_1..P:LABEL_2 7

Break when program memory location between P:LABEL_1 and P:LABEL_2 is written to 7 times (hardware breakpoint).

Example 10

BREAK pcm rw P:LABEL_1 7

Break when program memory location P:LABEL_1 is accessed 7 times (hardware breakpoint).

Example 11

BREAK xa r X:100

Break when data memory location 100 is read once (hardware breakpoint).

Example 12

BREAK xa r X:100 200

Break when data memory location 100 is read 200 times (hardware breakpoint).

Example 13

BREAK xa w X:100 200

Break when data memory location 100 is written to 200 times (hardware breakpoint).

Example 14

BREAK xa rw X:100 200

Break when data memory location 100 is accessed 200 times (hardware breakpoint).

Example 15

BREAK P:$228 T(AM_VALUE>#$1000)

Set a breakpoint at address P:228 and enter debug mode if the value of AM_VALUE is greater than $1000

Example 16

BREAK LOOP T(X0!=Y:$1200)

Set a breakpoint at program address labeled "LOOP" and enter debug mode if the value of register X0 is not equal to memory location Y:$1200.

Note: For DSP156 & 166 only P & X memory addressing are available.


CHANGE
CFORCE R

Reset the emulator hardware unit.  The CFORCE command is applicable only when the Debug-56K is used with an external emulation unit.

Example 1	CFORCE R

Reset the emulator


CHANGE
CHANGE[register]|[register_block]|[address]|[address_block](to) expression

CHANGE allows the modification of one of the following:

[register], one DSP or one OnCE register

[register_block],a block of DSP registers

[address], one memory location (data or program)

[address_block], a block of memory (data or program)

expression is the change value

Example 1

CHANGE X:0 10

Change data memory location 0 to 10

Example 2

CHANGE LABEL_1..LABEL_2 10

Change memory locations from LABEL_1 to LABEL_2 to 10

Example 3

CHANGE X:0#100 1234

Change 100 data memory locations starting at address  0 to 1234

Example 4

CHANGE Y:0#100 1234

Change 100 program memory locations starting at address  0 to 1234

Note: For DSP156 & 166 only P & X memory addressing are available.

Example 5: CHANGE A2 10        Change register A2 TO 10

Example 6: CHANGE A 255.99     Change register A TO 255.99

Example 7: CHANGE M0..M3 $FFFF Change addr. modifier registers M0-M3 to $ffff

Example 8: CHANGE OTC $4D2     Change the OnCE register OTC to 4D2 hex


CONFIG
CONFIG Refresh n|Tab n|Reset {On|Off} |Sens {On|Off} | Verify {On|Off} | Update {On|OfF}

The CONFIG Command is used to set the system options.

The CONFIG command is especially helpful when used with macro command files

Refresh:   Sets the minimum time delay (in ms) between screen refreshes in the continuous update mode.

Tab:       Sets the number of spaces for a tab character.  This applies only when displaying ASCII text files in the view window.

Reset:          When set, the DSP is automatically reset after a program load.  The default is off.

Sens:      Enables or disables case sensitivity for symbols entry.  The default is on.

Verify:         Enables or disables memory verify after memory writes.  Default is off.

Update:    Enables or disables the data and registers windows updates when the DSP is running.  Default is OFF.

Example 1

  CONFIG ref `2000

  Sets refresh interval time to 2000 ms (2 s)

Example 2

  CONFIG update on

  Turn automatic update ON.


COPY
COPY  (from) address_block (to) address

The COPY command copies one block of memory into another block. The source and destination maps may be different.

address_block is the block to be copied.

address is the starting address of the second block.

Example 1

COPY X:0..100 P:0

Copy data memory block 0 to 100 into program block starting at 0.

Example 2

COPY LABEL_1..LABEL_2 LABEL_3

Copy memory block LABEL_1 to LABEL_2 into memory block starting at LABEL_3.

Example 3

COPY X:0#100 X:200

Copy 100 memory locations starting at data memory location 0 into data memory location starting

at 200.


DISPLAY
DISPLAY [address]

The DISPLAY command displays program or data memory in the data window.

If more than one data window is open, the data is displayed in the window that "was last selected".

[address] is the starting address of the window. If [address] is not specified, the window is scrolled down by one page.

Example 1

DISPLAY LABEL_1

Display from memory location LABEL_1

Example 2

DISPLAY L:100

Display from memory location L:100

Note: For DSP156 & 166 only P & X memory addressing are available.

Example 3

DISPLAY P:100

Display from memory location P:100

Example 4

DISPLAY

Scroll active data window down by one page


DISASSEMBLE
DISASSEMBLE  [address][-mode]

The DISASSEMBLE command disassembles memory (program or data) in the Unassemble window.

[address] is the starting address of the window.  If [address] is not specified, the window is scrolled down by one page.

[-mode] is the display mode to be used for unassembly.  Available modes are: Asm, Mix, and Scr.

Example 1

DISASSEMBLE LABEL_1

Disassemble from memory location LABEL_1

Example 2

DISASSEMBLE X:100

Disassemble from memory location X:100

Example 3

DI P:100

Disassemble from memory location P:100

Example 4

DI

Scroll the Unassemble window down by one page


EMI
EMI [-wx] [-lx]

This command displays or sets EMI access parameters.

[-wx] - set EMI data bus width. For the data bus 4 bits wide specify -w0, for the data bus 8 bits wide -w1.

[-lx] - set EMI data word length. Here are four options to select:

      0	- 8 bit data word

      1	- 16 bit data word

      2	- 24 bit data word

      3	- 16 bit data word/24 bit data addressing

Example 1

EMI -L2

Set EMI data word length to 24 bits.

Example 2

EMI -W1 -L1

Set EMI data word length to 16 bits and data bus width to 8 bit.


EVALUATE
EVALUATE [lvalue=] rvalue

This command is used to evaluate expressions..

The EVALUATE command can also be used to re-define a variable, a memory location, or a register.  The EVALUATE command may be used with C and assembly language variables and constants.

lvalue =   Left Value. The left value and the equal sign are optional.  They are used when a variable or a memory location are re-defined.

rvalue     Right Value. The right value is the expression to evaluate.

The EVALUATE command is similar to the ? command, except the ? command displays the evaluated value in the command window.

Example 1	EVALUATE R0 = $100

Set register R0 to 100 hex

Example 2	EVALUATE R2 = (R0+R1) * 3

Evaluate the expression, set R2 to the result

Example 3	EVALUATE value_1 = value_2/value_3

Evaluate the expression, set value_1 to the result

Example 4	EVALUATE FILTER[100] = 0

Clear the 101's element of the array FILTER


FORCE
FORCE  R(reset to debug mode) | B(break) | RU(reset to user mode)

Reset or Break DSP

R	 Reset DSP and enter debug mode

B	 Stop DSP and enter debug mode

RU	 Reset DSP (Just toggle the DSP's reset line)

Function key Shift-F5 executes FORCE B.

Example 1

FORCE R

Reset DSP and enter debug mode

Example 2

FORCE B

Stop DSP and enter debug mode

Example 3

FORCE RU

Reset DSP and let run


GO
GO [address]

The GO command starts the execution of a DSP program.

If [address] is omitted, the program executes from the value of the Program Counter (PC), otherwise PC is changed to the [address] value

Function key F5 executes GO from the PC when the DSP is in stop mode.

Example 1

GO

Start DSP program execution from current program  counter.

Example 2

GO LABEL_1

Start DSP program execution from program memory  location LABEL_1.

Example 3

GO P:$100

Start DSP program execution from program memory location 100 hex.


HELP

Invokes help

When used with command name goes straight to the description of this command.


JUMP
JUMP [cont]

Jump over Subroutine Calls (F10)

JUMP is similar to single-step with the exception that JUMP instructs the DSP to treat a subroutine call as one instruction. This means that when executing a JUMP command and a subroutine call is encountered, the whole subroutine is executed. The subroutine calls may be conditional or unconditional.

If the DSP reaches a breakpoint inside the subroutine, it will enter the debug mode before completing the subroutine call.

[count] is the number of jumps to execute (default is 1 instruction and is equivalent to JUMP 1 command).  To end the JUMP command before the execution of all instructions, press Shift-F5 or execute a FORCE B command.

Example 1

JUMP

Execute jump.


INPUT
INPUT  [#(file number)] OFF |TERM | filename [-dec | -fra | -hex]

The input command is used to open a DOS file and use the file topass data to the target DSP chip.

The data is passed to the targetDSP when the user's program calls predefined block transfer subroutines in the EVM-SCI monitor code.

The INPUT command with no parameters displays all open input files.

[file number]  is the number of a file opened (multiple files canbe opened simultaneously).  The file number is optional, the rangeis 1 to 99.  The DOS file is always an ASCII file with the data listed sequentially. The file number assigned to the input streammust correspond to the file number used in DSP user program call to the monitor file input subroutines.

OFF closes an opened input file.  If a file is not specified, allopened files are closed.

TERM uses the terminal/keyboard (instead of a DOS file) to input data to the target DSP.

filename is the name of the DOS file used for data input.

-dec specifies decimal data representation

-fra specifies fractional data representation

-hex specifies hexadecimal data representation. This is the default.

Parameters specified by the user's DSP program

see also:

Details on the DOS file

Examples of DSP code to support the INPUT command

Example 1

INPUT

Display all currently open input files.

Example 2

INPUT #1 DATA.IO -dec

Open "DATA.IO" file, label it file number 1, and send the data to the DSP when the data transfer routine is called. Data in "DATA.IO" is in decimal.

Example 3

INPUT P:100 DATA.IN2

Open "DATA.IN2" file, label the file automatically, and send the data to the DSP when the breakpoint at address P:100 is reached. Data in "DATA.IN" is in hexadecimal.


LOAD
LOAD filename[.CLD][-S(ymbols)]

The LOAD command loads a program file generated by the Motorola assembler/linker into the DSP's internal and/or external memory.  Program as well as data memory are downloaded, as specified by the file.  The file is read from the default directory.(see PATHcommand)

filename[.CLD] is the name of the file. If the optional [.CLD] is not entered, it defaults to .CLD.  To load file in the OMF format,  LOD extension needs to be specified explicitly.

[-S(ymbols)] option will load only symbolic information from the specified file.

If the file loaded includes source line numbers information, LINK enters source level mode of operation. It will enable the mode selection button on top border of the Unassembly window.

If the file loaded includes a symbols table, LINK uses that table to refer to data and program memory. If a table is not available, LINK enters automatically into a non-symbolic mode of operation.

Example 1

LOAD DEMO1.CLD

Load the file DEMO1.CLD from the default path


LOG
LOG ON filename [.LOG] | OFF |MEM address_block | REG [reg_name]

The LOG command is used to log information to the log file .

ON filename [.LOG] will open the log file in the append mode.

Current date and time will be written to the log file.

OFF will close the log file. Before file is closed, current date and

time will be written to the file.

MEM address_block will save to the file contents of the

specified memory block.

REG will save contents of the DSP registers to the log file.

Example 1

LOG ON session5

Start logging to file SESSION5.LOG

Example 2

LOG MEM X:$40#$20

Save to log file 32 words of X memory


MAP
MAP [ON|OFF] | [addr_blk R|W|RW|PROTECT][-r]

Memory mapping control.

The MAP command allows for control of the memory mapping logic.

[ON|OFF] enables or disables memory mapping.

[addr_blk R|W|WR|PROTECT] add valid address range for specified memory accesses(Read, Write, ReacWrite or Protect)

[-r] delete entry from the memory map

If no parameters are specified, the memory map will be displayed.

Example 1

MAP on

Enable memory mapping

Example 2

MAP P:8000#4000 WR

Add ReadWrite entry to the memory map


OUTPUT
OUTPUT [#(file number)] [address] OFF | TERM | filename [-dec | -fra | -hex | -asc]

Assign Output File

The OUTPUT command is used to open a DOS file and use the file to save data passed from the target DSP chip.  The data is passed to the file when the user's DSP program reaches a software breakpoint.

The OUTPUT command with no parameters displays all open output files.

[file number]  is the number of a file opened (multiple files can be opened simultaneously).  The file number is optional, the range is 1 to 99.  The DOS file is always an ASCII file with the data listed sequentially.

[address] is the address of the debug instruction (always in the P: space). The address is optional if one of the direction bits in register R1 is set.

OFF closes an opened output file.  If a file is not specified, all opened files are closed.

TERM uses the terminal/monitor (instead of a DOS file), and display the data.

filename is the name of the DOS file used for data output.

-dec specifies decimal data representation

-fra specifies fractional data representation

-hex specifies hexadecimal data representation. This is the default.

-asc specifies ASCII type for "terminal" type output. Recognized are  following codes: CR, LF, TAB and BS. All other characters in ranges 0..$1f and $80..$ff are displayed as a '.' character.

Parameters specified by the user's DSP program

Examples on entering the input command

Example 1

OUTPUT

Display all currently open output files.

Example 2

OUTPUT #1 P:100 DATA.OUT -d

Open "DATA.OUT" file, label it file number 1, and use the file to save data when the breakpoint at address P:100 is reached. Data is saved in decimal.

Example 3

OUTPUT P:100 DATA.OUT

Open "DATA.OUT" file, label the file automatically, and send the data to the file when the breakpoint at address P:100 is reached. Data in "DATA.OUT" is in hexadecimal.

Example 4

OUTPUT P:100 TERM

When the breakpoint at P:100 is reached, read data from the DSP and send it to the terminal (screen).

see also:

Details on the DOS file

Examples of DSP code to support the OTPUT command


PATH
PATH [pathname]

The PATH command sets the default directory for file I/O.

If [pathname] is omitted, the current path is displayed (if it was previously set).

Example 1

PATH \56002\PROGRAMS\

SET the default directory to \56002\PROGRAMS\

Example 2

PATH

Display the path


QUIT

The QUIT command terminates LINK program execution.

The DSP is left in it's current state and the screen configuration (LINK's screen configuration) is automatically saved into the file LINK.CFG (or the file specified with command line option  -g  ).  This file is used to determine screen configuration for the next invocation of LINK.

Alt-X may also be used to terminate LINK

Example 1

QUIT

Quit LINK


RADIX
RADIX B(binary) | D(decimal) | F(fractional) | H(hexadecimal)

Change Default Input Number Base (F2)

The RADIX command changes the default input base number of the Command window, it affects entering addresses as well as constants. The default radix is displayed on the top border of the command window.

The radix may be overwritten if one of the following characters precedes a number:

$    for hexadecimal numbers (example $7fffff)

`    for decimal numbers (example `5000)

%    for binary numbers (example %10101011)

When the Command window is selected, Function key F2 may be used to change the default radix.

The RADIX command can not be used to change the radix of a data or a register window.

Example 1

RADIX H

Set default radix to hexadecimal

Example 2

RADIX B

Set default radix to binary


REFRESH
REFRESH [ON|OFF]

Disables or enables windows refresh flag

Disabling will speed-up execution of macro commands.


RETURN

Run the DSP until a RETURN instruction is reached.

The DSP is stopped when a RET instruction is reached.

Example 1

RETURN

Execute DSP, stop when a RET instruction is reached.


SAVE
SAVE addr_block [addr_block] [addr_block] ... filename[.LOD]

The SAVE command saves a block (or blocks) of memory into a DOS file.

The file format is compatible with files generated by the Motorola assembler/linker. Program as well as data memory can be saved. Memory can be internal or external to the DSP.

If the file directory is not specified, the file is read from the default directory (see the PATH command). If the file extension is not specified, it is automatically assumed to be .LOD

Symbols are not saved with the SAVE command.

Example 1

SAVE x:0..90 DATA.001

Save memory locations x:0 to x:90 into file "DATA.001"

Example 2

SAVE x:0..90 P:0..100 DATA.002

Save memory locations x:0 to x:90 and memory locations P:  to P:100 into file "DATA.002"


STEP
STEP [count]

The STEP command instructs the DSP to execute [count] number of instructions and then enter the debug mode.

The instructions start executing from the current value of the program counter.  After the execution of the [count] instructions, the DSP enters the debug mode and the screen is refreshed (the DSP gets no interruptions while it is executed the instructions).

If [count] is not specified, it defaults to one.

Example 1

STEP

Execute one DSP instruction and enter the debug mode.

Example 2

STEP 5

Execute 5 DSP instructions and enter the debug mode.

Example 3

STEP `65000

Execute 65,000 DSP instructions and enter the debug mode.


SYMBOL
SYMBOL[name|part of symbol name]

The SYMBOL command displays the symbols used in the DSP program, in alphabetical order.

If [name|part of symbol name] is omitted, all symbols are displayed.  Symbols are case sensitive.

Example 1

SYMBOL

Display all symbols

Example 2

SYMBOL La

Display all symbols starting with La

Example 3

SYMBOL Label

Display all symbols starting with Label


TIME

Display Execution Time

The TIME command will display time of last execution period.  Timer is set when GO command is sent and reset on breakpoint entry or forced break.  Resolution of the timer is 1 μs.  For proper timer operation, the program should be run for the time greater than 50 μs.

Example 1

TIME

Display timer value from last GO


TRACE
TRACE [count]

The TRACE command executes a single or multiple DSP instructions with a full screen refresh after every instruction.

[count] is the number of instructions to execute (default is 1 instruction and is equivalent to STEP 1 command).  To end the TRACE command before the execution of all instructions, press Shift-F5 or execute a FORCE B command.

Function key F8 executes one trace. Function key Shift-F8 executes an infinite number of traces.

Example 1

TRACE

Execute one DSP instruction and update screen

Example 2

TRACE 10

Execute 10 DSP instructions with a screen update after every instruction

Example 3

TRACE '60000

Execute 60,000 instructions with a screen update after every instruction


UNALIAS
UNALIAS name|key

The UNALIAS command deletes an alias and its definition.

This is also used to remove user defined buttons(remember to use the full name preceded with an exclamation sign ("!")

Example 1

UNALIAS prgload

Remove "PRGLOAD" alias

Example 2

UNALIAS !man

Remove "man" alias and the user "man" button


UNASSEMBLE
UNASSEMBLE [address] [-mode]

UNASSEMBLE - disassembles memory (program or data) in the Unassemble window.

[address] is the starting address of the window.  If [address] is not specified, the window is scrolled down by one page.

[-mode] is the display mode to be used for unassembly.  Available modes are: Asm, Mix and Src.

Example 1

UNASSEMBLE LABEL_1

Disassemble from memory location LABEL_1

Example 2

UNASSEMBLE X:100

Disassemble from memory location X:100

Example 3

U P:100

Disassemble from memory location P:100

Example 4

U

Scroll the Unassemble window down by one page


UNTIL
UNTIL [address]

Execute DSP Program

The UNTIL command starts the execution of a DSP program.

[address] specifies location of the temporary breakpoint.

If address is specified, execution is performed until this address is reached.

Example 1

UNTIL 100

Execute code until address 100 is reached(temporary breakpoint).


USE
USE  [path string [-r]]

The USE command specifies additional directory to be searched for the source files.

Multiple directories can be specified, but only one at a time. If no parameters are specified, all defined directories will be listed.

[-r] option will remove specified directory from the search list.

Example 1

USE d:\dsp\source\coeff

Use additional directory while locating source file


VARIABLE
VARIABLE  name

Define a New Variable

The variable command defines a variable at the debugger level.  The variable defined may then be used for temporary storage.   The variable is defined on the PC, at the debugger level and not on the DSP.

name       The name of the variable defined

Example 1

VARIABLE PC_STORAGE	; define a new variable

? PC_STORAGE = PC  	; save PC value

GO                 	; start DSP

FORCE R            	; stop DSP

? PC = PC_STORAGE  	; restore PC value


VERSION

Display Debug-56K's revision in the command window.

Example 1

VERSION

Will display following string in the Command window:

LINK56xxx microcode version: x.xx.


VIEW
VIEW filename [line #]

Open ASCII file

The VIEW command is used to display a DOS ASCII file in the Text Window.

filename is the name of the file to display in the Text Window. If a directory is not specified within the file name, the default directory is used (see the PATH command).

[line #] is optional and is used to specify the first line to display (default to 1).

The VIEW command closes a previously opened file to display the new file.

Example 1

VIEW DEMO1.ASM

Open the file "DEMO1.ASM" in the Text Window and display it starting at line 1.

Example 2

VIEW DEMO1.ASM 10

Open the "DEMO1.ASM" in the Text Window and display it starting at line 10.


WAIT
WAIT [time | BREAK]

Wait Specified Time

The WAIT command is used for macro command processing.  It allows for time delay or synchronization

If no parameters are specified, command execution will be suspended until any key is pressed.

time specifies delay in seconds for command processor to wait. If key is pressed, WAIT will be aborted.

BREAK command processor will wait until DSP gets in debug mode of operation.

Example 1

WAIT 12

Suspend command execution for 12 seconds

Example 2

WAIT break

Wait until DSP enters debug mode.


WATCH
WATCH expression,[label],[-hex | -dec | -fra | -bin | -remove]

Define Watch Variable

The WATCH command places a variable, register or expression in the watch window.

expression can be symbol, address, register or 'C' type expression.

[-hex|-dec|-fra|-bin] is the radix used for the display. The default is hex.

label will be displayed in the front of the watch, instead of the address.

-remove is used to remove a variable from the watch window. If an address/symbol is not specified, all the watched variables are removed.

Example 1

WATCH X:$0000

Place memory location at X:0000 in the watch window.

Example 2

WATCH AM_VALUE,,-bin

Place memory location at AM_VALUE in the watch window, display in binary.

Example 3

WATCH AM_VALUE,, -r

Remove memory location AM_VALUE from the watch window.

Example 4

WATCH AM_VALUE * SPEED,Coef

Add expression to the watch window, and display it with the label 'Coef'

Example 5

WATCH ,,-r

Remove all watched variables from the watch window.


?

Evaluate Expression

?          ( [ lvalue = ] rvalue )

The ? command is used to evaluate expressions.  The result of the expression evaluation is displayed in the command window.  The ? command can also be used to change the value of a variable, a memory location, or a register.  The ? command may be used with C and assembly language variables and constants.

lvalue =   Left Value.  The left value and the equal sign are optional, they are used when a variable or a memory location are modified.

rvalue          Right Value.  The right value is the expression to evaluate.

The ? command is similar to the EVALUATE command, except the EVALUATE command does not display the evaluated value.

Example 1	? R0 = $100

Set register R0 to 100 hex, display new R0

Example 2	? A

Display the value of register A

Example 3	? R2 = (R0+R1) * 3

Evaluate the expression, set R2 to the result, display new R2

Example 4	? value_1 = value_2/value_3

Evaluate the expression, set value_1 to the result, display new value_1

Example 5	? FILTER[100] = 0

Clear the 101's element of the array FILTER, display new 101's element of array FILTER.6    REFERENCES


Macro Command

Macro Command processor will open the text file MacroName(.CMD) and process its contents.  Macro command file is built with text editor.  It can have any combination of valid commands.  Command is processed until new line, end of file or semicolon(;) is found.  When command is finished, macro command processor will read next line.

Example 1

radix hex

wait break	;wait until DSP gets in debug mode

change x:0#10 0	;clear first 16X memory locations

go	;start execution

force b	;stop execution

wait break	;wait until DSP gets in debug mode

trace	;trace next instruction

wait break	;wait until DSP gets in debug mode

break p:7C	;set breakpoint

go

wait break	;wait until DSP gets in debug mode

time	;display execution time


Entry Rules
Command Entry Rules

1.	Only one, two, or three letters of a command need to be typed when entering a command.  This feature is designed to reduce the number to keystrokes needed to enter a command.

Example:  C PC 0     is equivalent to:  CHANGE PC 0

2.	The radix of the command window determines the default input radix.  This affects constants as well as addresses being entered.  The default radix may be overwritten by preceding a number by: ` for decimal, $ for hexadecimal, and % for binary.

3.	A block of memory may be specified in two ways:

Format 1: The memory block is defined by the starting address and the ending address of the block:

Syntax:   start_address..end_address

Example:  CHANGE X:0..$FF $123456   Will change memory locations 0 to $FF to $123456

Format 2: The memory block is defined by the starting address of the block and the number of words in the block.

Syntax:   start_address#number_of_words

Example:  CHANGE X:0#100 $123456     Will change 100 memory locations starting at 0  to 100 to $123456)

4.	A register block defines a block of DSP registers  The block of registers is defined by the first register and the last register of the block.

Syntax:  start_register..end_register

Register blocks possible:

X0..X1,

Y0..Y1,

A0..A2,

B0..B2,

R0..R7,

N0..N7,

M0..M7,

Example:  CHANGE R0..R7 $1234 Will change registers R0, R1, ..R7 to $1234.


Command Help Rules

The last line displays command specific help when a command is being entered.  The following is the command help convention:

A list of the commands is made available by pressing the space bar repeatedly.

The highlighted part of a command name indicates the least letters that need to be types when entering a command.

Parameters between brackets [] are for optional parameters.

Example:  GO [address]

Parameters between parentheses () are for descriptive purposes only.

Example:  COPY (from) address_block (to) address

A bar |  is used to separate a list of possible command parameters.

Example:  FORCE     R | B | RU


Commands Entry
Command Editor

To speed-up commands entry, the command window has a built-in command editor.  The mouse and the following keys may be used when a command is being entered or edited.

Key	Description

↑↓	Scroll through command history buffer

←  →	Move cursor left and wright

Ins	Toggle insert mode On Off

Del	Delete a character

Home	Move to beginning of command line

End	Move to end of command line

Esc	Delete changes

Enter	Accept and execute command

The horizontal scroll-bar can also be used to scroll through the command history buffer.

The pull down menu(config, command) can be used to programm the command window.


Function Keys

F1:  Get help

F2:  Change radix or change program display mode

F3:  Display data grafically(on/off)

F5:  Start execution (Go)

F6:  Next window

F7:  Go to the line

F8:  Step

F9:  Breakpoint(set/clear)

F10: Jump over call

SF5: Stop execution

SF6: Automatic screen update(on/off)

SF8: Continuous step(on/off)

SF10:Continuous jump(on/off)

Definitions of every key can be changed with ALIAS command.


Software Breakpoints

For the software breakpoints there are 16 types of condition based on the Condition Code Register (CCR) bit values. LINK replaces your opcode with DEBUGcc DSP instruction to set a conditional software breakpoint. Thus program may be contaminated. Extreme care must be observed when using these breakpoints.

Break_type	Meaning       	Condition Code Bit(s)

CC	carry clear    	C = 0

CS	carry set     	C = 1

EC	extension clear	E = 0

EQ	equal          	Z = 1

ES	extension set  	E = 1

GE	greater or equal	N xor V = 0

GT	greater than   	Z or (N xor V) = 0

LC	limit clear    	L = 0

LE	less or equal  	Z or (N xor V) = 1

LS	lower or same  	Z or C = 1

LT	less than      	N and V = 1

MI	minus          	N = 1

NE	not equal      	Z = 0

NR	normalized     	Z or (not N and not E) = 1

PL	plus           	N = 0

NN	not normalized 	Z or (not N and not E) = 0


Hardware
Hardware Breaks

Break types for DSP56001 and 56002

pcf	Break on program memory fetch.

pcm	Break on program memory move.

pcfm	Break on program memory read/write.

pce	Break on executed fetches only.

pa	Break on P memory access

xa	Break on X memory access

ya	Break on Y memory access

Break types for DSP56156 and 56166

pcf	Break on program memory fetch.

pcm	Break on program memory (r,w,or rw)

xab1	Break on data memory(r,w, or rw)

xab2	Break on second data memory move(r,w, or rw)


pcf
pcf	Break on program memory fetch

It is the fetch of the instruction to be executed

(in the case of conditional jumps or calls)

the breakpoint in not performed.

For two word instructions, the break

 occurs at the fetch of the first

opcode(if the condition is satisfied).


pcm
pcm	Break on program memory (r,w,or rw)

This applies to all program memory move

instruction including program fetches,

that are not executed and the second word

of a two word instruction. r,w,or rw

is specified by break_access.


xab1
xab1	Break on data memory(r,w, or rw)

For a two move instruction,

the break is performed

when the first move is satisfied.

r,w, or rw is specified by break_access.


xab2
xab2	Break on second data memory move(r,w, or rw)

Break on second data memory move(r,w, or rw)

of a two move instruction. r,w, or rw

is specified by break_access.

Parameters specified by the user's DSP program

 Since multiple files can be opened, your DSP program must specify the file number, this is accomplished by placing the file number in the most significant 8 bits of register X0.

 The user program must specify the number of words to transfer, this is accomplished by placing that number in the low 16 bits of register X0.  The low 8 bits of register X0 are used for the DSP56100.

 The user program must also specify the address where the data will be placed.  This is accomplished by placing that address in register R0.

 The user program must specify the address space (P:, X: or Y:) where the data will be placed. This is accomplished by placing a value in the register R1. A 0 is used for P:, 1 for X: and 2 for Y: memory space.

 The direction of the data transfer may be specified (optional) by placing a flag in register R1. If the most significant bit (8000 hex) is 1, the direction is into the DSP. If the 14th bit (4000 hex) of R1 is 1, direction is out of the DSP. If neither bits are set, the address of the DEBUG instruction is used.

 The breakpoint must reached by a user induced DEBUG instruction.


Break_Access

Break_access type  Meaning:

   r               breakpoint for read

   w               breakpoint for write

   rw              breakpoint for read or write (access)


DETAILS ON THE DOS FILE

The DOS file is always ASCII, with the data listed sequentially. LINK provides ways to simplify the file editing (for example if one word must be send to the DSP repeatedly, you can have a repeat code instead of typing an infinitely long file. The following are the codes that may be used in the ASCII file

     #    Specifies the number of times a data word is repeated.

    ( )   Parenthesis are used to group words. If parenthesis are preceded by # the whole group is repeated. If # doest not precede the parenthesis, the group of words is repeated indefinitely.

EXAMPLE 1

0.1  0.2  0.3  0.4

Send data words 0.1, 0.2, 0.3, 0.4.

EXAMPLE 2

0.1#10

Send the data words 0.1 10 times.

EXAMPLE 3

(0.1 0.2)#10

Send 0.1, 0.2, 0.1, 0.2 ....

EXAMPLE 4

(7FFF)

Send 7FFF indefinitely

EXAMPLE 5

1 2 3 5#2 (10 20)#3 (10)

send 1, 2, 3, 5, 5, 10, 20, 10, 20, 10, 20, 10, 10,

10, 10, ...


Examples of DSP to support the INPUT command
Examples of DSP code to support the INPUT command

EXAMPLE 1:

MOVE $010010,X0	;16 words from file NUMBER1(for DSP56100: MOVE $0110,X0)

MOVE $0000, R0	;place data at address 0

MOVE $0001, R1	;place the data in space X:

DEBUG	;Break and enter the DEBUG mode

EXAMPLE 2:

MOVE $020012,X0	;18 words from file NUMBER2(for DSP56100: MOVE $0210,X0)

MOVE $0020, R0	;place data at address 20

MOVE $0000, R1	;place the data in space P:

DEBUG	;Break and enter the DEBUG mode

EXAMPLE 3:

MOVE $030080,X0	;128 words from file NUMBER3(for DSP56100: MOVE $0380,X0)

MOVE $0200, R0	;read data at address 200HEX

MOVE $8002, R1	;read the data in space Y:

DEBUG	;Break and enter the DEBUG mode


Examples of DSP to support the output command
Examples of DSP code to support the OUTPUT command

EXAMPLE 1:

MOVE $010010,X0	;16 words from file NUMBER1(for DSP56100: MOVE $0110,X0)

MOVE $0000, R0	;read data at address 0

MOVE $0001, R1	;read the data fromspace X:

DEBUG	;Break and enter the DEBUG mode

EXAMPLE 2:

MOVE $020012,X0	;18 words from file NUMBER2(for DSP56100: MOVE $0210,X0)

MOVE $0020, R0	;read data at address 20

MOVE $0000, R1	;read the data fromspace P:

DEBUG	;Break and enter the DEBUG mode

EXAMPLE 3:

MOVE $030080,X0	;128 words from file NUMBER3(for DSP56100: MOVE $0380,X0)

MOVE $0200, R0	;read data at address 200HEX

MOVE $4002, R1	;read the data fromspace Y:

DEBUG	;Break and enter the DEBUG mode


56300 list of registers
DSP5300 Registers LIST

Core:

 DALU

 ADDRESS GENERATION UNIT

 EXPANSION PORT CONTROL

 PROGRAM CONTROL UNIT

 DMA CONTROLLER

 PLL Clock Oscillator

 OnCE

Peripherals:

 HOST INTERFACE 08

HOST Interface (HI32):

  HOST_SIDE

  DSP_SIDE

 GPIO

 SCI

 ESSI

 TIMER


56300 Data ALU
56300 Data ALU Registers

 A2:A1:A0    	Data ALU Accumulator Register A

 B2:B1:B0    	Data ALU Accumulator Register B

 X1:X0, Y1:Y0	Data ALU Input Register


56300 Address Generation Unit
56300 Address Generation Unit Registers

 R0..R7      	Address Register

 N0..N7      	Offset Register

 M0..M7      	Modulo Register

 EP          	Stack Extension Pointer


56300 Expansion Port Control
56300 Expansion Port Control Registers

 BCR         	Port A Bus Control Register

 AAR         	Port A Address Attribute Register(AAR3-AAR0)

 DCR         	DRAM Control Register


56300 Program Control Unit
56300 Program Control Unit Registers

 PC      	Program Counter Register

 LA      	Loop Address Register

 LC      	Loop Count Register

 SC      	Stack Count Register

 SZ      	Stack Size Register

 SSH     	System Stack High

 SS1     	System Stack Low

 VBA     	Vector Base Address Register

 SP     	Stack Pointer Register

 SR     	Status Register

 OMR   	Operating Mode Register

 IPRC 	Interrupt Priority Register C

 IPRP 	Interrupt Priority Register P

 IDR 	Device Identification (ID) Register


56300 DMA Controller
56300 DMA Controller Registers

 DMA_DCR(5-0)	DMA Control Register(channel 5-0)

 DMA_DSTR   	DMA Status Register

 DMA_DOR(3-0)	DMA Offset Registers

 DMA_DCO(5-0)	DMA Counter(channel 5-0)

 DMA_DSR(5-0)	DMA Source Address Register (channel 5-0)

 DMA_DDR(5-0)	DMA Destination Address Register(channel 5-0)


56300 PLL Registers
56300 PLL Clock Oscillator Registers

 PCTL         	PLL Control


56300 OnCE REGISTERS

 OSCR   	OnCE Status and Control Register

 OBCR   	OnCE Breakpoint Control Register

 OTAGBSR	OnCE Cache Tag LRU/LOCK Status Register

 OMBC   	OnCE Memory Breakpoint Counter

 OMLR   	OnCE Memory Limit Register

 OGDBR  	OnCE Global Data Bus Register

 OPDBR  	OnCE Program Data Bus Register

 OPILR  	OnCE Program Instruction Latch Register

 OTC    	OnCE Trace Counter

 OTAGB  	OnCE Cache Tag Register

 OPABFR 	OnCE Program Address Bus Register

 OPABDR 	OnCE Program Address Bus Decode Register

 OPABEX 	OnCE Program Address Bus Execute Register

 OFIFO  	OnCE Program Address Bus Fifo Register

 OGDB  	OnCE GDB Register; X:$FFFFFC


56300 Host Interface 08 Registers
56300 HOST INTERFACE 08

 HPCR	Port Control Register

 HDDR	Direction Register.

 HDR	Data Register.

 CVR    	Read-Write Command Vector Register. Host Processor Address

 HCR    	Control Register

 HBAR   	Base Address Register

 HSR    	Status Register

 HTX    	Transmit Data Register

 HRX    	Receive Data Register

 ICR    	R/WInterrupt Control Register. Host Processor Address 0.

 ISR    	R-Only Interrupt Status Register.Host Processor Address 2.

 IVR   	R/W Interrupt Vector Register. Host Processor Address 3.

 RXH   	Read-Only Receive Byte Reg. (High). Host Proc. Addr. 5/7.",

 RXM   	Read-Only Receive Byte Reg. (Mid). Host Proc. Addr. 6.",

 RXL   	Read-Only Receive Byte Reg. (Low). Host Proc. Addr. 5/7.",

 TXH   	Write-Only Transmit Byte Reg. (High). Host Proc. Addr. 5/7.",

 TXM   	Write-Only Transmit Byte Reg. (Mid). Host Proc. Addr. 6.

 TXL   	Write-Only Transmit Byte Reg. (Low). Host Proc.Addr. 5/7.",


56300 Host Side Registers
56300 (HI32) HOST SIDE REGISTERS

 CBMA      	Memory Space Base Address Configuration Register.",

 CCCR/CRID 	Class Code/Revision Id  Configuration Register.},

 CDID/CVID 	Device/Vendor Id Configuration Register.},

 CHTY/CLAT 	Header Type/Latency Timer Register.",

 CSTR/CCMR 	Status/Command Configuration Register

 CILP      	Interrupt Line-Interrupt pin Configuration Register

 HSTR      	Host Interface Status Register

 HTXR      	Host Transmit Data Reg.-Write-only 32-bit

 HCTR      	Host Interface Control Register.

 HCVR      	Host Command Vector Register.

 HRXM        	Host Master Receive Data Reg. Read-only 32-bit

                  The HRXM can't be accessed by the NDE Core or the host.

 HSXM        	Host Slave Receive Data Reg. Read-only 32-bit rec. data reg.


56300 DSP Side Registers
56300 (HI32)DSP SIDE REGISTERS

 DCTR	DSP Control Register.

 DPCR	DSP PCI Address Register.

 DPMC	DSP PCI Master Control Register.

 DPAR	DSP PCI Address Register.

 DSR 	DSP Status Register.

 DPSR	DSP PCI Status Register.

 DATH	DSP Host Port GPIO Data Register.

 DIRH	DSP Host Port GPIO Direction 24-bit Register

 DRXR	DSP Receive Data Register.

 DTXM	DSP Master Transmit Data Register.

 DTXS	DSP Slave Transmit Data Register.


56300 GPIO Port Registers
56300 GPIO REGISTERS

 PCRC 	DSP Port C Control Register.

 PRRC	DSP Port C Direction Register.

 PDCR	DSP Port C GPIO Data Register.

 PCDR	DSP Port D Control Register.

 PRRD	DSP Port D Direction Register.

 PDRD	DSP Port D GPIO Data Register.

 PCRE	DSP Port E Control Register.

 PRRE	DSP Port E Direction Register.

 PDRE	DSP Port E GPIO Data Register.


56300 SCI REGISTERS

 SCCR	Clock Control Register.

 SCR 	Control Register.

 SSR 	Status Register.

 SRXH	Receive Data Register High.	X:$FFFF9A

 SRXM	Receive Data Register Middle.	X:$FFFF99

 SRX1	Receive Data Register Low.	X:$FFFF98

 STXH	Transmit Data Register High.	X:$FFFF97

 STXM	Transmit Data Register Middle.X:$FFFF96

 SRX1	Transmit Data Register Low.	X:$FFFF95

 STXA	Transmit Address Register.	X:$FFFF94


56300 ESSI REGISTERS

 CRA	Control Register A.

 CRB	Control Register B.

 SSISR	Status Register.

 RX    	Serial Receive Register

 TSR  	Time Slot Register.

 TX0..TX2 	Serial Transmit Register 0,1, & 2

 TSMA,TSMB	Transmit Slot Mask Register A & B.

 RSMA,RSMB	Receive Slot Mask Register A & B


56300 TIMER REGISTERS

 TPLR 	Timer Prescaler Load Register.

 TPCR 	Timer Prescaler Count Register.

 TCSR 	Timer Control/Status Register.

 TCR  	Timer Count Register.

 TLR  	Timer Load Register.

 TCPR 	Timer Compare Register.


56300 Port A Bus Control Register
56300 Port A Bus Control Register BCR

X:$FFFFFB Read/Write   24-bit Register

Bit:

 4..0     BA0W4..BA0W0	Area 0 wait states

 9..5     BA1W4..BA1W0	Area 1 wait states

12..10    BA2W2..BA2W0	Area 2 wait states

15..13    BA3W2..BA3W0	Area 3 wait states

20..16    BDFW4..BDFW0	Default area wait states

21        BBS	Bus State

22        BLH	Bus Lock hold

23        BRH	Bus Request hold


56300 Port A Address Attribute Register
56300 Address Attribute Registers AAR3-AAR0

X:$FFFFF9 Read/Write   32bit Register  AAR0

X:$FFFFF8 Read/Write   32bit Register  AAR1

X:$FFFFF7 Read/Write   32bit Register  AAR2

X:$FFFFF6 Read/Write   32bit Register  AAR3

Bit:

 1,0       BAT1,BAT0	External Access Type

 2         BAAP	AA pin polarity

 3         BPEN	Program Space Enable

 4         BXEN	X Data Space Enable

 5         BYEN	Y Data Space Enable

 6         BAM	Address Muxing

 7         BPAC	Packing Enable

11..8      BNC3..BNC0	Number of Address bit to compare

31..12     BAC11  BAC0	Address to Compare


56300 DRAM Control Register
56300 DRAM Control Register  DCR

X:$FFFFFA Read/Write   24-bit Register

Note:  The programmer must guarantee that all the DCR bits except BSTR are not changed while accessing a DRAM !

Bit:

1,0       BCW1-BCW0	In Page Wait States

3,2       BRW1-BRW0	Out of Page Wait States

7..4	Reserved

8,9       BPS1-BPS0	DRAM Page Size

10	Reserved

11        BPLE	Page Logic Enable

12        BME	Mastership Enable

13        BREN	Refresh Enable

14        BSTR	Software Triggered Refresh

22..15    BRF7-BRF0	Refresh Request Rate

23        BRP	Refresh Prescaler


56300 DMA Control Register
56300 DMA Control Register DCR(5-0)

X:$FFFFEC Read/Write   24-bit Register  DCR0

X:$FFFFE8 Read/Write   24-bit Register  DCR1

X:$FFFFE4 Read/Write   24-bit Register  DCR2

X:$FFFFE0 Read/Write   24-bit Register  DCR3

X:$FFFFDC Read/Write   24-bit Register  DCR4

X:$FFFFD8 Read/Write   24-bit Register  DCR5

Bit:

1,0       DSS1-DSS0	DMA Source Memory Space

3,2       DDS1-DDS0	DMA Destination Memory Space

9..4      DAM5-DAM0	Address Generation Mode

9,8       BPS1-BPS0	DRAM Page Size

10        D3D	3 & non 3 dimensional medes

15..11    DRS4-DRS0	DMA Request Source

16        DCON	MDMA Continuous Mode

18..17    DPR1-DPR0	DMA Channel Priority

21..19    DTM2-DTM0	DMA Transfer Mode

22        DIE	DMA Interrupt Enable Bit

23        DE	DMA Channel Enable Bit


56300 DMA Status Register
56300 DMA Status Register DSTR

X:$FFFFF4 Read/Write   24-bit Register

Bit:

5..0       DTD5-DTD0	DMA Transfer Done Status Bits

6,7       	Reserved

8         DACT	DMA Ac

8,9       BPS1-BPS0	DRAM Page Size

10        D3D	3 & non 3 dimensional medes

15..11    DRS4-DRS0	DMA Request Source

16        DCON	MDMA Continuous Mode

18,17     DPR1-DPR0	DMA Channel Priority

21..19    DTM2-DTM0	DMA Transfer Mode

22        DIE	DMA Interrupt Enable Bit

23        DE	DMA Channel Enable Bit


56300 DMA OFFSET Register
56300 DMA OFFSET RegisterS DOR(3-0)

X:$FFFFF3 Read/Write   24-bit Register DOR0

X:$FFFFF2 Read/Write   24-bit Register DOR1

X:$FFFFF1 Read/Write   24-bit Register DOR2

X:$FFFFF0 Read/Write   24-bit Register DOR3

This register contains the offset value to be used in some of the DMA addressing modes. Registers DOR0-DOR3 can be used by all the channels according to their address generation mode.


56300 DMA Counter Register
56300 DMA Counter Registers DCO(5-0)

X:$FFFFED Read/Write   24-bit Register DCO0

X:$FFFFE9 Read/Write   24-bit Register DCO1

X:$FFFFE5 Read/Write   24-bit Register DCO2

X:$FFFFE1 Read/Write   24-bit Register DCO3

X:$FFFFDD Read/Write   24-bit Register DCO4

X:$FFFFD9 Read/Write   24-bit Register DCO5

This register contains the number of DMA data transfers to be done. The DCO has five modes of operations deteermined by the DMA channel's address deneration mode that are defined in the DMA channel's Control Register


56300 DMA Source Address Register
56300 DMA Source Address Registers DSR(5-0)

X:$FFFFEF Read/Write   24-bit Register DSR0

X:$FFFFEB Read/Write   24-bit Register DSR1

X:$FFFFE7 Read/Write   24-bit Register DSR2

X:$FFFFE3 Read/Write   24-bit Register DSR3

X:$FFFFDF Read/Write   24-bit Register DSR4

X:$FFFFDB Read/Write   24-bit Register DSR5

This register contains the source for the next DMA transfer. The DMA controller has one source address register for each DMA channel.


56300 DMA Destination Address Register
56300 DMA Destination Address Registers DRR(5-0)

X:$FFFFEF Read/Write   24-bit Register DDR0

X:$FFFFEA Read/Write   24-bit Register DDR1

X:$FFFFE6 Read/Write   24-bit Register DDR2

X:$FFFFE2 Read/Write   24-bit Register DDR3

X:$FFFFDE Read/Write   24-bit Register DDR4

X:$FFFFDA Read/Write   24-bit Register DDR5

This register contains the destination address for the next DMA transfer. The DMA controller has one source address register for each DMA channel.


56300 Interrupt Priority Register C
56300 IPRC Interrupt Priority Register C

X:$FFFFFF    24-bit Register

IPRC Register is dedicated for the DSP56300 Core interrupt sources

Bit:

2..0      IAL2-IAL0	IAL2: IRQ A Mode/ IAL1:0 IRQ A IPL

5..3      IBL2-IBL0	IBL2:IRQ B Mode/ IBL1:0 IRQ B IPL

8..6      ICL2-ICL0	ICL2: IRQ C Mode/ ICL1:0 IRQ C IPL

11..9     IDL2-IDL0	IDL2: IRQ D Mode/ IDL1:0 IRQ D IPL

13,12     D0L1-D0L0	DMA 0 IPL

15,14     D1L1-D1L0	DMA 1 IPL

17,16     D2L1-D2L0	DMA 2 IPL

19,18     D3L1-D3L0	DMA 3 IPL

21,20     D4L1-D4L0	DMA 4 IPL

23,22     D5L1-D5L0	DMA 5 IPL

Interrupt priority level bits

xxL1	xxL0	Enabled	IPL

0	0	No	----

0	1	Yes	0

1	0	Yes	1

1	1	Yes	2

External Interrupt trigger Mode Bits:

IxL2	Trigger Mode

1	Negative Edge

0	Level


56300 Interrupt Priority Register P
56300 IPRP Interrupt Priority Register P

X:$FFFFFE   24-bit Register

IPRP Register is dedicated for the specific chip peripherals interrupt sources

Bit:

Bit:

1,0       HPL1,HPL0	HI32 IPL for 56301 or HI08 IPL for 56303

3,2       SOL1,SOL0	ESSI0 IPL

5,4       S1L1,S1L0	ESSI1 IPL

7,6       SCL1,SCL0	SCI IPL

9,8       T0L1,T0L0	Triple Timer IPL

23..10   	reserved

xxL1	xxL0	Enabled	IPL

0	0	No	----

0	1	Yes	0

1	0	Yes	1

1	1	Yes	2


56300 Device Identification Register
56300 IDR DEVICE IDENTIFICATION Register

X:$FFFFF5  Read Only 24-bit Register  Reset =

Bit:

11..0       Derivative Number(001100000001) This is the number for the DSP56301

15..12      Rev.Number(001) This is the revision number for the DSP56301 first silicon

23..16      Zeros(00000000)


56300 Operating Mode Register
56300 OMR Program Controller Operating Mode Register

COM(7:0)	Chip Operating Mode byte

Bit:

3..0    MD..MA	Operating Mode x, x=D:A

4       EBD	External Bus Disable

5       	Reserved

6       SD	Stop Delay

7       MS	Memory Switch Mode

EOM(15:8)	Extended Chip Operating Mode byte

Bit:

9,8     CDP1,CDP0	Core Dma Priority x, x=1:0

10      BE	Burst Mode Enable

11      TAS	TA Synchronize Selected

12      BRT	Bus Release Timing

15..13   	Reserved

15      ATE	only in 56302

SCS(22:16)	System Stack Control Status byte

Bit:

16      XYS	Stack Extension Space Select

17      EUN	Extended Stack Underflow Flag

18      EOV	Extended Stack Overflow Flag

19      WRP	Extended Stack Wrap Flag

20      SEN	Stack extension Enable

21,22   	Reserved

DSP56303 and 56301 Operating modes


56300 Operating Modes

Mode	MOD(D/C/B/A)	Reset Vector	Description

0	0000	$C00000	Expanded mode [1]

1	x001	$FF0000	Bootstrap from byte-wide memory

2	x010	$FF0000	Bootstrap thru SCI

3	x011	-------	Reserved

4	x100	$FF0000	for 56303:HI08 Bootstrap ISA Mode for 56301:Host Bootstrap PCI Mode(32-bit wide)

5	x101	$FF0000	for 56303:HI08 Bootstrap in HC11 nonmultiplex mode for 5301:Host Bootstrap 16-bit wide UB Mode (ISA)

6	x110	$FF0000	for 56303: HI08 Bootstrap in 8051 multiplex bus mode for 5301: Host Bootstrap 8-bit wide UB Mode in double-strob pin configuration

7	x111	$FF0000	for 56303: HI08 Bootstrap in 68302 bus mode

for 5301: Host Bootstrap 8-bit wide UB Mode in single-strob pin configuration

8	1000	$008000	Expanded mode

Note:1. Address $C00000 is reflected as $00000 on Port A pins A0-A17


56300 Stack Pinter Register
56300 SP Stack Pointer Register

Bit:	Non Extended Mode/Extended Mode

3..0    P3-P0	Stack Pointer

4       SE/P4	Stack Error Flag/Stack Pointer P4

5       UF/P5	Underflow Flag/Stack Pointer P5

23..6   P23-P6	Stack Pointer P23:P6


56300 Status Register
56300 SR Status Register

CCR(7:0)	Condition Code Register

Bit:

0     C	Carry

1     V	Overflow

2     Z	Zero

3     N	Negative

4     U  	Unnormalized

5     E 	Extension

6     L 	Limit

7     S 	Scaling Bit

MR(15:8)	Mode Register

9,8     I1,I0	Interrupt Mask bit1:0

11,10   S1,S0	Scaling Mode Bit1:0

12       	Reserved

13      SC	Sixteen Bit Compatibility

14      DM	Double Precision Multiply

15      LF	DO-Loop Flag

EMR(23:16)	Extended Mode Register

16      FV	DO-Forever Flag

17      SA	Sixteen Bit Arithmetic

18       	Reserved

19      CE	Instruction Cache Enable

20      SM	Arithmetic Saturation

21      RM	Rounding Mode

23,22   CP1,CP0	Core Priority Bit1:0


56300 PLL Control Register
56300 PCTL  PLL Control Register

X:$FFFFFD    24-bit Register

Bit:

11..0    MF11-MF0	Multiplication Factor Bits

14..12   DF2-DF0	Division Factor Bits

15       XTLR	Crystal Range Bit

16       XTLD	Disable Bit

17       PSTP	STOP Processing State Bit

18       PEN	PLL Enable Bit

19       COD	Clock Output Bit

23..20   PD3-PD0	PreDivider Factor Bits


56300 Port Hi08 Host Port Control Register HPCR
56300 Hi08 Port Control Register HPCR

X:$FFFFC4   Read/Write 16-bit Register

Bit:

0	HGEN	Host GPIO Port Enable

1	A8EN	Host Address Line 8 Enable

2	HA9EN	Host Address Line 9 Enable

3	HCSEN	Host Chip Select Enable

4	HHREN	Host Request Enable

5	HAEN	Host Acknowledge Enable

6	HEN	Host Enable

7	reserved

8	HROD	Host Request Open Drain

9	HDSP	Host Data Strobe Polarity

10	HASP	Host Address Strobe Polarity

11	HMUX	Host Multiplexed Bus

12	HDDS	Host Dual Data Strobe

13	HCSP	Host Chip select Polarity

14	HRP	Host Request Polarity

15	HAP	Host Acknowledge Polarity


56300 Port Hi08 Host Data Direction Register HDDR
56300 Hi08 Data Direction Register HDDR

X:$FFFFC4   Read/Write 16-bit Register

The HDDR Controls the direction of each of the HI08 pins configured as GPIO. Note that even when the HI08 is used as the host interface, some of its pins may be configured as GPIO pins and the direction of these pins is controlled by this register.

Bit:

15..0	DR15-DR0

DRx=1 the corresponding HI08 pin is configured as an output pin.

DRx=0 the corresponding HI08 pin is configured as an input pin


56300 Port Hi08 Host Data Register HDR
56300 Hi08 Data Direction Register HDR

X:$FFFFC9   Read/Write 16-bit Register

The HDR holdss the data value of the corresponding bits of the HI08 pins which are configured as GPIO pins.The Dxx functionality depends on the corresponding HDDR bit. the HDR can not be accessed by the host processor.

Bit:

15..0	D15-D0

DRx

0(input)	  Dx as GPIO pin is the read only bit. The valuue read is the binary value of the pin; Dx as a non-GPIO pin is the read only pin. Does not contain significant data

1(output)	Dx as GPIO pin is read/write bit. The value written is the value read.The corresponding pin is configured as an output, and is driven with the data written to Dxx.. Dx as a non-GPIO pin is a read/write bit. The value written is the value read.


56300 HI08 R-W Command Vector Register HCVR
56300 HI08 R-W Command Vector Register CVR

Bit:

0      HHC    	Host Command

7..1   HV6-HV0	Host Command Vector

14..8         	reserved

15     HNMI   	Host Nonmaskable Interrupt

31..16         	reserved


56300 HI08 Control Register HCR

X:$FFFFC2   Read/Write 16-bit Register

Bit:

0	HRIE	 Host Receive Interrupt Enable

1	HTIE	 Host Transmit Interrupt Enable

2	HCIE	 Host Commant Interrupt Enable

4..3	HF3-HF2 Host flags

7..5	      	reserved


56300 HI08 Base Address Register HBAR

X:$FFFFC5   Read/Write 16-bit Register

Bit:

7..00	BA10-BA03


56300 HI08 Status Register HSR

X:$FFFFC3   Read only 16-bit Register

Bit:

0    	HRDF	 Host Receive Data Full

1    	HTDE	 Host Transmit Data Empty

2    	HCP 	 Host Command Pending

4,3 	HF1,HF0 Host Flags

15..5	reserved


56300 HI08 Host TransmitRegister
56300 HI08 Host Transmit Register HTX

X:$FFFFC7 Write only 24-bit Register

The HTX register is used for DSP to host data transfers. Writing the HTX registers clears HTDE. The DSP may program the HTIE bit to cause a host transmit data interrupt when HTDE is set. The HTX register is transferred as 24-bit data to the receive byte registers(RXMH:RXM:RXL) if both the HTDE bit and receive data full(RXDF status bits are cleared.This transfer operation sets RXDF and HTDE. Data should not be written to the HTx until HDTE is set to prevent the previous data from being overwritten.


56300 HI08 Host Receive Register
56300 HI08 Host Receive HRX

X:$FFFFC6 Read only 24bit Register

The HTX register is used for host to DSP data transfers.The HRX register is loaded with 24-bit data from the transmit registers (TXH:TXM:TXL) on the host side when both the transmit data register empty (TXDE) and DSP host receive data full(HRDF) bits are cleared. This transfer operation sets TXDE and HRDF. The HRX register contains valid data when HRDF bit is set. Reading HRX clears HRDF. The DSP may program the HRIE bit to cause a host receive data interrupt when HRDF is set.


56300 HI08 R/W Interrupt Controll Register
56300 HI08 R/W Interrupt Controll Register 	ICR

Host Processor Address 0

Bit:

0    	HREQ

1    	TREQ

2    	HDRQ

4..3	HF1-HF0

5    	HBEND

6    	reserved

7    	INIT


56300 HI08 R-Only Interrupt Status Register
56300 HI08 R-Only Interrupt Status Register ISR

Host Processor Address 2

Bit:

0   	RXDF

1   	TXDE

2   	TRDY

4..3	HF3-HF2

6..5	       	reserved

7   	HREQ


56300 Memory Space Base Address Configuration Register CBMA
56300 (HI32) Memory Space Base Address Configuration Register CBMA

Bit:

0      MSI      	Memory Space Indicator

2..1   MS1-MS0  	Memory Space(Hardwired to zeros)

3      PF       	Pre-fetch(Hardwired to zero)

15..4  PM15-PM4 	Memory Base Address Low(Hardwired to zeros)

31..16 PM31-PM16	Memory Base Address High

23..16 GB10-GB3 	Universal Bus mode Base Address


56300 Class Code/Revision Id Configuration Register CCCR
56300 (HI32) Class Code/Revision Id Configuration Register CCCR

Bit:

7..0            	Non implemented. read/write as 0

15..8  LT7-LT0  	Latency Timer  High

23..16 HT7-HT0  	Header type(hardwires to $00)

31..16 PM31-PM16	Memory Base Address High

31..24          	Non implemented. read/write as 0


56300 Device/Vendor ID Configuration Register CDID/CVID)
56300 (HI32) Device/Vendor ID Configuration Register CDID/CVID

Bit:

15..0   VID15-VID0	Vendor ID  hardwired $1057

31..16  DID15-DID0	Device ID  via programable


56300 Header Type/Latency Timer Configuration Reg.CHTY/CLAT
56300 (HI32)Header Type/Latency Timer Configuration Register CHTY/CLAT

Bit:

7..0   	reserved Read/Write As 0

15..8  LT7-LT0	Latency Timer( High)

23..16 HT7-HT0	Header Type(hardwired to 0)

31..24 	reserved Read/Write As 0


56300 Status/Command Configuration Register CSTR/CCMR
56300 (HI32)Status/Command Configuration Register CSTR/CCMR

CCMR:

Bit:

0	    	not implemented Read/Write As 0

1	 MSE 	Memory Space Enable

2	 BM  	Bus Master Enable

5..3        	not implemented Read/Write As 0

6	 PERR	Parrity Error Response

7	 WCC 	Wait Cycle Control ( hardwired to 0)

8	 SERE	System Error Enable

9           	not implemented Read/Write As 0

15..10      	reserved Read/Write As 0

CSTR

22..16          	reserved Read/Write As 0

23	FBBC     	Fast Back-to-Back Capable ( hardwired to 0)

24	DPR      	Data Parity Reported

26..25 DST1-DST0	DEVSEL Timing ( hardwired to 0)

27	STA      	Signaled Target Abort

28	RTA      	Received Target Abort

29	RMA      	Receive Master Abort

30	SSE      	Signaled System error

31	DPE      	Detected Parity Error


56300 Interrupt Line-Interrupt Pin Configuration Reg.CILP
56300 (HI32)Interrupt Line-Interrupt Pin

Configuration Register CILP

Bit:

7..0	IL7-IL0	Interrupt Line

15..8	IP7-IP0	Interrupt Pin

23..16	MG7-MG0	MIN_GNT

31..24	ML7-ML0	MAX_LAT


56300 Host Status Register HSTR
56300 (HI32)Host Status Register HSTR

Bit:

0   	TRDY	Transmitter Ready

1   	HTRQ	Host Transmit Data Request

2   	HRRQ	Host Receive Data Request

5..3	HF5-HF3   	Host Flags

6	HINT	Host Interrupt A

7	HREQ	Host Request

31..8	reserved


56300 Host Interface Control Register HCTR
56300 (HI32)Host Interface Control Register HCTR

Bit:

0   	reserved

1   	TREQ

2   	RREQ

4..3	HF1-HF0

5   	DHF2

6   	HMAE

7   	SFT

9..8	HTF1-HTF0

10  	reserved

12..11 HRF1-HRF0

13	reserved

16..14 HS2-HS0

18..17 reserved

19	TWSD

31..20 reserved


56300 Host Command Vector Register HCVR
56300 (HI32)Host Command Vector Register HCVR

0      	HC

7..1   	HV6-HV0

14..8  	reserved

15     	HNMI


56300 DSP Side Control Register DCTR
56300 (HI32)DSP Side Control Register DCTR

X:$FFFC5    24-bit Register  Reset =

Bit:

0	HCIE   	Host Command Interrupt Enable

1	STIE   	Slave Transmit Interrupt Enable

2	SRIE   	Slave Receive Interrupt Enable

5..3   HF5-HF3	Host Flags

6	HINT   	Host Interrupt A

12 :7 	       	reserved Read/Write As 0

13	HDSM   	Host Data Strobe Mode

14	HRWP   	Host RD/WR Polarity

15	HTAP   	Host Transfer Acknowledge Polarity

16	HDRP   	Host DMA Request Polarity

17	HRSP   	Host Request Polarity

18	HIRH   	Host Interrupt Request Handshake Mode

19	HIRD   	Host Interrupt Request Drive Control

22..20 HM2-HM0	HI32 Mode

23 	reserved Read/Write As 0


56300 DSP Side PCI Address Register DPAR
56300 (HI32)DSP Side PCI Address Register DPAR

X:$FFFC8    24-bit Register  Reset =

Bit:

15..0  	AR15-AR0 	DSP PCI Transaction Address (Low)

19..16 	C3-C0    	PCI Bus Command

23..20 	!BE3-!BE0	PCI Byte Enables


56300 DSP Side PCI Control Register DPCR
56300 (HI32)DSP Side PCI Control Register DPCR

X:$FFFC6    24-bit Register  Reset =

Bit:

0	    	reserved

1	MTIE	Master Transmit Interrupt Enable

2	MRIE	Master Receive Interrupt Enable

3	    	reserved

4	MAIE	Master Address Interrupt Enable

5	PEIE	Parity Error Interrupt Enable

6	    	reserved

7	TAIE	Transaction Abort Interrupt Enable

8	    	reserved

9	TTIE	Transaction Termination Interrupt Enable

11,10	    	reserved

12	TCIE	Transfer Complete Interrupt Enable

13	    	reserved

14	CLRT	Clear Transmitter

15	MTT	Master Transfer Terminate

16	SERF	!HSERR Force

17	    	reserved

18	MACE	Master Access Counter Enable

19	MWSD	Master Wait State Disable

20	RBLE	Receive Buffer Lock Enable

21	IAE 	Insert Address Enable

23,22	 	    	reserved


56300 DSP Side PCI Master Control Register DPMC
56300 (HI32)DSP Side PCI Master Control Register DPMC

X:$FFFC7    24-bit Register  Reset =

Bit:

15..0 	AR31-AR16	DSP PCI Transaction Address (High)

21..16	BL5-BL0  	PCI Data burst Length

23,22	FC1-FC0  	Data Transfer Format Control


56300 DSP Side PCI Status Register DPSR
56300 (HI32)DSP Side PCI Status Register DPSR

X:$FFFCA    24-bit Register  Reset =

Bit:

0	MWS       PCI Master Wait States

1	MTRQ      PCI Master Transmit Data Request

2	MRRQ      PCI Master Receive DataRequest

3	          reserved

4	MARQ      PCI Master Address Request

5	APER      PCI Address Parity Error

6	DPER      PCI Data Parity Error

7	MAB       PCI Master Abort

8	TAB       PCI Target Abort

9	TDIS      PCI Target Disconnect

10	TRTY      PCI Target Retry

11	TO        PCI Time Out Termination

12	HDTC      PCI Host Data Transfer Complete

15..13           reserved

21..16 RDC5-RDC0 Remaining Data Count

23,22  	   reserved


56300 DSP Side Status Register DSR
56300 (HI32)DSP Side Status Register DSR

X:$FFFC9    24-bit Register  Reset =

Bit:

0	HCP	Host Command Pending

1	STRQ	Slave Transmit Data Request

2	SRRQ	Slave Receive Data Request

5..3	HF2-HF0	Host Flags

22..6	reserved

23	HACT	HI32 Active


56300 DSP Side Host Port GPIO Data Register DATH
56300 (HI32)DSP Side Host Port GPIO Data Register DATH

X:$FFFCF    24-bit Register  Reset =

Note: DATH is used by the DSP56300 Core to read or write data to/from host port pins configured as GPIO. the DATH cannot be accessed by the host processor.

Bit:

23..0	DATx     GPIO Pin Data     x=23,...,0


56300 DSP Side Host Port GPIO Direction Register DIRH
56300 (HI32)DSP Side Host Port GPIO Direction Register DIRH

X:$FFFFCE    24-bit Register  Reset =

Note: DIRH is used by the DSP56300 Core to control the direction of the host port pins in GPIO mode. The DIRH cannot be accessed by the host processor.

DIR23-DIR0 are used to define the corresponding GPIO pins as input or output.

Bit:

23..0	DIRx     GPIO Pin Direction     x=23,...,0

DIRx= 0 :

- GPIO pin;  read only bit; the value read is the binary value of the pin. The corresponding pin is configured as an input.

- non GPIO;  read only bit; does not contain significant data

DIRx= 1 :

- GPIO pin;  read/write bit;the value written  is the value read; the corresponding pin is configured as an output, and is driven with the data to DATx

- non GPIO;  read/write bit;the value written  is the value read;


56300 DSP Side Host Port Receive Data FIFO Register
56300 (HI32)DSP Side Host Port Receive Data FIFO   DRXR

X:$FFFFCB  read only 24-bit Register

The DRXR contains master data (i.e. data read by the HI32 as PCI master from an external target) to be read if MPRQ is set in DPSR. MPRQ is cleared if the data in the DRXR is slave data or when the host-to-DSP data path FIFO is emptied by DSP56300  Core reads. the DSP56300 Core may set the MRIE bit to cause a host receive data interrupt when MRRQ is set.

The DRXR contains slave data (i.e. data written by the HI32 from the host bus) to be read if SRRQ is set in the DSR. SRRQ is cleared if the data in the DRCR is master data or when the host-to-DSP data path FIFO is emptied by DSP56300 Core reads. the DSP56300 Core may set the SRIE bit to cause a host receive data interrupt when SRRQ is set.

In the 32-bit mode(HM=$1,FC=$0 or HT=$0) only the two least significant bytes contain data, the most significant byte is read as zeroes.


56300 DSP Side Master Transmit Data Register DTXM
56300 (HI32)DSP Side Master Transmit Data Register   DTXM

X:$FFFFCC  Write only 24-bit Register

The DTXM-24-bit DSP master transmit data register is the input stage of the master DSP-to-host data path FIFO used for DSP-to-host master data transfers in the PCI mode(HM=$1).

The DTXM may be written if the MTRQ bit is set in the DPSR. Data should not be written to the DTXM until MTRQ is set to prevent previous data from being overwritten. Filling the DTXM by DSP56300 Core writes ( MOVE(P) instruction or DMA transfers) clears MTRQ. The DSP56300 Core may set the MTIE bit to cause a host receive data interrupt when MTRQ is set.

In the PCI mode (HM=$1) the DSP56300 Core can clear the HI32 master-to-host bus data path and empty DTXM by setting the CLRT bit in the DPCR.

In the 32-bit mode (HM=$1, FC=$0) only the two least significant bytes of the DTXM are transferred.


56300 DSP Side Slave Transmit Data Register DTXS
56300 (HI32)DSP Side Slave Transmit Data Register   DTXS

X:$FFFFCD  Write only 24-bit Register

The DTXS-24-bit DSP slave transmit data register is the input stage of the slave DSP-to-host data path FIFO used for DSP-to-host slave data transfers in the PCI mode(HM=$1).

The DTXS may be written if the STRQ bit is set in the DSR. Data should not be written to the DTXS until STRQ is set to prevent previous data from being

overwritten. Filling the DTXS by DSP56300 Core writes ( MOVE(P) instruction or DMA transfers) clears STRQ. The DSP56300 Core may set the STIE bit to cause a host receive data interrupt when STRQ is set.

In the 32-bit mode (HM=$1, HRF=$0) only the two least significant bytes of the DTXS are transferred.


56300 GPIO Port Control Register PCR
56300 GPIO Port Control Register  PCR(C,D,E)

X:$FFFFBF  read/write 16-bit register  PCRC---port C

X:$FFFFAF  read/write 16-bit register  PCRD---port D

X:$FFFF9F  read/write 16-bit register  PCRE---port E

Port Control Register PCR(C,D,E for corresponding ports) controls the functionality of ESSI GPIO pins.  When the PCR is read to the internal data bus, the register contents occupy the two low-order bytes of the data bus, and the remaining bits are read as zeros. When  written the most significant byte should be written zero for future compbility.

Bit:

5..0	PC5-PC0	Port Control Bits: 1 ESSI, 0 GPIO

15..6	reserved


56300 GPIO Port Direction Register PRR
56300 GPIO Port Direction Register  PRR(C,D,E)

X:$FFFFBE  read/write 16-bit register  PRRC---port C

X:$FFFFAE  read/write 16-bit register  PRRD---port D

X:$FFFF9E  read/write 16-bit register  PRRE---port E

Port Direction Register PRR(C,D,E for corresponding ports) controls the direction of ESSI GPIO pins.  When the PRR is read to the internal data bus, the register contents occupy the two low-order bytes of the data bus, and the remaining bits are read as zeros. When written the most significant byte should be written zero for future compbility.

Bit:

5..0	PDC5-PDC0	Direction Control Bits: 1 Output, 0 Input

15..6	reserved


56300 GPIO Port Data Register PRR
56300 GPIO Port Data Register  PDR(C,D,E)

X:$FFFFBD  read/write 16-bit register  PDRC---port C

X:$FFFFAD  read/write 16-bit register  PDRD---port D

X:$FFFF9D  read/write 16-bit register  PDRE---port E

Port Data Register PRR(C,D,E for corresponding ports) is used to read or write data to/from ESSI GPIO pins. Bits PD(5:0) are used to read or write data from/to the corresponding pins if they are configured as GPIO (by PC(5:0) bits in PCR). If a port pin[i] is configured as a GPIO input, then the corresponding PD[i] bit will reflect the value present on this pin.  If a port pin[i] is configured  as a GPIO output, then the value written into the corresponding PD[i] bit will reflected on this pin. When the PDR is read to the internal data bus, the register contents occupy the two low-order bytes of the data bus, and the remaining bits are read as zeros. When written the most significant byte should be written zero for future compbility.

Bit:

5..0	PD5-PD0

15..6	reserved


56300 SCI Clock Control Register SCCR

X:$FFFF9B read/write 16-bit register

Bit:

11..0	CD11-CD0	SCCR Clock Divider

12	COD	SCCR Clock Out Divder

13	SCP	SCCR SCI Clock Prescaler

14	RCM	SCCR Receive Clock Mode Source

15	TCM	SCCR Transmit Clock Source


56300 SCI Control Register SCR

X:$FFFF9C read/write 24-bit register

Bit:

2..0	WDS2-WDS0	SCR Word Select

3   	SSFTD    	SCI Shift Direction

4   	SBK      	SCR Send Break

5   	WAKE     	SCR Wakeup Mode Select

6   	RWU      	SCR Receiver Wakeup Enable

7   	WOMS     	SCR Wired-OR Mode Select

8   	RE       	SCR Receiver Enable

9   	TE       	SCR Transmitter Enable

10  	ILIE     	SCR Idle Line Interrupt Mode

11  	RIE      	SCR Receive Interrupt Enable

12  	TIE      	SCR Transmit Interrupt Enable

13	TMIE     	SCR Timer Interrupt Enable

14	STIR     	SCR Timer Interrupt Rate

15	SCKP     	SCR SCI Clock Polarity

16	REIE     	SCR SCI Receive with Exception Interrupt Enable

23..17          	reserved; read / write as zero


56300 SCI Status Register SSR

X:$FFFF93 Read only 8-bit register

Bit:

0   	TRNE	SSR Transmitter Empty

1   	TDRE	SSR Transmit Data Register Empty

2   	RDRF	SSR receive Data Register Full

3   	IDLE	SSR Idle Line Flag

4   	OR  	SSR Overrun Error Flag

5   	PE  	SSR Parity Error

6   	FE  	SSR Framing Error Flag

7   	R8  	SSR Received Bit (R8) Address


56300 ESSI Control Register CRA

X:$FFFFB5 Read/Write  24-bit register CRA0 /ESSI0/

X:$FFFFA5 Read/Write  24-bit register CRA1 /ESSI1/

CRA Register is used to direct the operation of the ESSI. CRA controls the ESSI clock generator bit and frame sync rates, word lengh,and number of words per frame for the serial data.

Bit:

7..0  	PM7..PM0	CRA Prescale Modulus Select

10..8 	reserved (read/write as zero)

11    	PSR     	CRA Prescaler Range

16  12	DC4-DC0	CRA Frame Rate Divider Control

17    	reserved read as zero and should be written as zero

18    	ALC    	CRA Alignment Control

21..19	WL2-WL0	CRA word Length Control

23    	reserved read as zero and should be written as zero


56300 ESSI Control Register CRB

X:$FFFFB6 Read/Write  24-bit register CRB0 /ESSI0/

X:$FFFFA6 Read/Write  24-bit register CRB1 /ESSI1/

CRB Register is used to direct the operation of the ESSI. CRB controls the ESSI multifunction pins,SC2, SC1, andSC0, which can be used as clock inputs or outputs, frame synchronization pins, transmit data pins or serial I/O flag pins.

Bit:

1,0    	OF1,OF0  	CRB Serial Output Flag 1,0

4..2   	SCD2-SCD0	CRB Serial Control (2,1,0) Direction Bit

5      	SCKD     	CRB Clock Source Direction

6      	SHFD     	CRB Shift Direction

8,7    	FSL1,FSL0	CRB Frame Sync Length

9      	FSR      	CRB Frame Sync Relative Timing

10     	FSP      	CRB Frame Sync Polarity

11     	CKP      	CRB Clock Polarity

12     	SYN      	CRB Synchronous/Asynchronous

13     	MOD      	CRB ESSI Mode Select

16..14	TE0-TE2  	CRB ESSITransmit #0,#1,#2 Bit

17     	RE       	CRB ESSI Receive Enable

18     	TIE      	CRB ESSI Transmit Interrupt Enable

19     	RIE      	CRB ESSI Receive Interrupt Enable

20     	TLIE     	CRB ESSI Transmit Last Slot Interrupt Enable

21     	RLIE     	CRB ESSI Receive Last Slot Interrupt Enable

22     	TEIE     	CRB ESSI Transmit Exception Interrupt Enable

23     	REIE     	CRB ESSI Receive Exception Interrupt Enable


56300 ESSI Status Register SSISR

X:$FFFFB7 Read only  8-bit register SSISR0 /ESSI0/

X:$FFFFA7 Read only  8-bit register SSISR1 /ESSI1/

SSISR is an 8-bit status register used by the DSP to read the status and serial input flags on the ESSI. When thr SSISR is read to the internal data bus, the register contents occupy the low-order byte of the data bus, and the remaining bits are read as zeros.

Bit:

1,0    	IF1,IF0  	SSISR Serial Interrupt Flag 1,0

2      	TFS      	SSISR Transmit Frame Sync Flag

3      	RFS      	SSISR Receive Frame Sync Flag

4      	TUE      	SSISR Transmitter Underrun Error Flag

5      	ROE      	SSISR Receiver Overrun Error Flag

6      	TDE      	SSISR ESSI Transmit Data Register Empty

7      	RDF      	SSISR ESSI Receive Register Full


56300 ESSI Receive Data Register RX

X:$FFFFB8 Read only  24-bit register RX0 /ESSI0/

X:$FFFFA8 Read only  24-bit register RX11 /ESSI1/

RX accepts data from the receive shift register as it becomes full. The data will occupy the most significant portion of the receive data register according to ALC settings(ALC=0 the mbs is bit 23 and when ALC=1 the mbs bit is 15)The unused bits will read as zeroes. the DSP is interrupted whenever RX becomes full if the associated interrupt is enabled.


56300 ESSI Time Slot Register TSR

X:$FFFFB9 Write only  24-bit register TSR0 /ESSI0/

X:$FFFFA9 Write only  24-bit register TSR1 /ESSI1/

TSR is effectivelly a null  data register that is used when the data is not to bbe transmitte in the available transmit time slot. For the purpose of timing, TSR is a write only register that behaves like an alternative transmit data register, except that, rather than transmitting data, the transmit data pins of all the enabled transmitters are in the high-impedance state for that time slot.


56300 ESSI Transmit Data Registers TX2,TX1,TX0
56300 ESSI Transmit Dataisters TX0,TX1,TX2

X:$FFFFBC Write only  24-bit register TX00 /ESSI0/

X:$FFFFBB Write only  24-bit register TX01 /ESSI0/

X:$FFFFBA Write only  24-bit register TX02 /ESSI0/

X:$FFFFAC Write only  24-bit register TX00 /ESSI1/

X:$FFFFAB Write only  24-bit register TX01 /ESSI1/

X:$FFFFAA Write only  24-bit register TX02 /ESSI1/

Data  to be transmitted is written into TX2, TX1, and TX0 registers and is automatically transferred to the transmit shift registers. The data written(8,12 , 16, or 24 bits) should occupy the most significant portion of the TXx according to ALC settings(ALC=0 than mbs=23; ALC=1 than mbs=15). The unused bits of the TXx are don't care bits. The DSP is interrupted whenever the TXx becomes empty if the transmit data register interrupt has been enabled.


56300 ESSI Transmit Slot Masks TSMA, TSMB
56300 ESSI Transmit Slot Mask Registers TSMA,TSMB

X:$FFFFB4 Read/Write  16-bit register TSMA0 /ESSI0/

X:$FFFFB3 Read/Write  16-bit register TSMB0 /ESSI0/

X:$FFFFA4 Read/Write  16-bit register TSMA1 /ESSI1/

X:$FFFFA3 Read/Write  16-bit register TSMB1 /ESSI1/


56300 ESSI Receive Slot Masks RSMA, RSMB
56300 ESSI Receive Slot Mask Registers RSMA,RSMB

X:$FFFFB2 Read/Write  16-bit register TSMA0 /ESSI0/

X:$FFFFB1 Read/Write  16-bit register TSMB0 /ESSI0/

X:$FFFFA2 Read/Write  16-bit register TSMA1 /ESSI1/

X:$FFFFA1 Read/Write  16-bit register TSMB1 /ESSI1/


56300 Timer Prescaler Load Register TPLR

X:$FFFF83 Read/Write   24-bit Register

The TPLR controls the prescaler divide factor and the source for the prescaler input clock.

Bit:

20...0 	PL20-PL0	Timer Prescaler Preload Value Bits

22,21  	PS1,PS0   	Timer Prescaler Source Bits

23     	          	reserved read as zero and should be written as zero


56300 Timer Prescaler Count Register TPCR

X:$FFFF82 Read only   24-bit Register

The TPCR reflects the current value in the prescaler counter.

Bit:

20.. 0 	PC20-PC0	Timer Prescaler Counter Value Bits

23..21 	        	reserved read as zero and should be written as zero


56300 Timer Control/Status Register TCSR

X:$FFFF8F Read/Write  24-bit Register TCSR0

X:$FFFF8B Read/Write  24-bit Register TCSR1

X:$FFFF87 Read/Write  24-bit Register TCSR2

The TCSR controls the timer and reflects its status

Bit:

0   	TE     	Timer Enable

1   	TOIE   	Timer Overflow Interrupt Enable

2   	TCIE   	Timer Compare Interrupt Enable

3   	       	reserved read as zero and should be written as zero

7..4	TC3-TC0	Timer Control Bits

8   	INV    	Inverter

9   	TRM    	Timer Reload Mode

10  	       	reserved read as zero and should be written as zero

11  	DIR    	Direction

12  	DI     	Data Input

13  	DO     	Data Output

14  	       	reserved read as zero and should be written as zero

15  	PCE    	Prescaled Clock Enable

19..16        	reserved read as zero and should be written as zero

20  	TOF    	Timer Overflow Flag

21  	TCF    	Timer Compare Flag

23,22	       	reserved read as zero and should be written as zero


56300 Timer Count Register TCR

X:$FFFF8C Read only  24-bit Register TCR0

X:$FFFF88 Read only  24-bit Register TCR1

X:$FFFF84 Read only  24-bit Register TCR2

In Timer and Watchdog Modes the counter contents can be read at any time by reading the TCR register.  In Measurements Modes the TCR will be loaded with the current value of the counter on the appropriate edge of the input signal and its value can be read to determine the width, period or delay of leading edge of the input signal (incoming on the TIO pin).


56300 Timer Load Register TLR

X:$FFFF8E Write only  24-bit Register TLR0

X:$FFFF8A Write only  24-bit Register TLR1

X:$FFFF86 Write only  24-bit Register TLR2

In all modes the counter is preloaded with the TLR value after the Timer Enable bit is set (TE=1) and a first event occurs.

In Timer modes, if timer reload mode is set (TRM=1), the counter is reloaded each time after it has reached the value contained by the TCR and the new event occurs.

In Measurement Modes, if timer reload mode   s set (TRM=1), the counter is reloaded with the  TLR value on each appropriate edge of the input signal, after the Tmer Enable bit is set (TE=1).

In PWm modes, if timer reload mode is set ( TRM=1), the counter is realoaded each time after it has overflowed and the new event occurs.

In watchdog Modes, if timer reload is set (TRM=1), the counter is reloaded each time after it has reached the value contained by the Timer Compare Register and the new event occurs. In this mode, the counter is reloaded whenever the TLR is written with a new value while the TE=1.

In all modes, if TRM is cleare(TRM=0), the counter operates as free running counter.


56300 Timer Compare Register TCPR

X:$FFFF8D Read/Write  24-bit Register TCPR0

X:$FFFF89 Read/Write  24-bit Register TCPR1

X:$FFFF85 Read/Write  24-bit Register TCPR2

TCP

TCPR contains the value to be compared to the counter value. The counter value is compared against the value contained by the TCPR an every timer clock after the Timer Enable bit is set(TE=1)

When the  compare matches, the TCF bit is set and, if interrupts are enabled(TCIE=1), an interrupt is generated. In Measurement Modes the TCPR is ignored.


56300 OnCE Status And Control Register OSCR

Bit:

0   	TME     	Trace Mode Enable

1   	IME     	Interrupt Mode Enable

2   	SWO     	Software Debug Occurrence

3   	MBO     	Memory Breakpoint Occurrence

4   	TO      	Trace Occurrence

5   	HIT     	Cache Hit

7,6 	OS1,OS0 	Core Status Bits

23..8          	reserved read as zero and should be written as zero


56300 OnCE Breakpoint Control Register OBCR

Bit:

1,0    	MBS1,MBS0	Memory Breakpoint Select Bits

3,2    	RW01,RW00	Breakpoint 0 Read/Write Select Bits

5,4    	CC01,CC00	Breakpoint 0 Read/Write Select Bits

7,6    	RW11,RW10	Breakpoint 1 Read/Write Select Bits

9,8    	CC11,CC10	Breakpoint 1 Read/Write Select Bits

11,10  	BT1,BT0  	Breakpoint 0 and 1 Event Select Table

23..12	         	reserved read as zero and should be written as zero


56300 OnCE Cache Tag LRU/LOCK Status Register OTAGBSR

Bit:

7..0	  0

8   	LOCK7

9   	LRU7

.   	.

.   	.

.   	.

20  	LOCK1

21  	LRU1

22  	LOCK0

23  	LRU0