Copyright: Copyright ® Domain Technologies, Inc. 1998


Contents
DSP56362 REGISTERS

Core:

Expansion Port and DRAM Controller

Data ALU

Address Generation Unit

Program Control Unit

DMA Controller

PLL Clock Oscillator

OnCE   On-chip Emulator

JTAG    Test Access Port

Peripherals:

Host Port:   HDI08

Serial Host Interface SHI

Enhanced Serial Audio Interface: ESAI

DIGITAL AUDIO TRANSMITTER: DAX

Tripple Timer Module

Internal I/O Memory Map


Expansion Port  and DRAM Control
Expansion Port Control

 BCR           Port A Bus Control Register

 AAR           Port A Address Attribute Register(AAR3-AAR0)

 DCR          DRAM Control Register


BCR Register
BCR Register - Port A Bus Control

X:$FFFFFB Read/Write   24-bit Register

Bit:
 4..0       BA0W4..BA0W0	Area 0 wait states
 9..5       BA1W4..BA1W0	Area 1 wait states
12..10    BA2W2..BA2W0	Area 2 wait states
15..13    BA3W2..BA3W0	Area 3 wait states
20..16    BDFW4..BDFW0	Default area wait states
21          BBS	Bus State
22          BLH	Bus Lock hold
23          BRH	Bus Request hold


AAR Registers

X:$FFFFF9 Read/Write   32bit Register  AAR0
X:$FFFFF8 Read/Write   32bit Register  AAR1
X:$FFFFF7 Read/Write   32bit Register  AAR2
X:$FFFFF6 Read/Write   32bit Register  AAR3

Bit:
 1,0         BAT1,BAT0	External Access Type
 2            BAAP	AA pin polarity
 3            BPEN	Program Space Enable
 4            BXEN	X Data Space Enable
 5            BYEN	Y Data Space Enable
 6            BAM	Address Muxing
 7            BPAC	Packing Enable
11..8       BNC3..BNC0	Number of Address bit to compare
31..12     BAC11  BAC0	Address to Compare


DRAM Control Register DCR

Bits:
1-0       BCW1,BCW0      In page wait states
3-2       BRW1,BRW0      Out of Page wait states
10,7-4  RESERVED
9-8        BPS1, BPS0       DRAM Page Size
11         BPLE                  Page logic Enable
12         BME                   Master Enable
13         BREN                 Refresh Enable
14         BSTR                 Software triggered Refresh
22-15    BRF7-BRF0         Refresh Request Rate
23         BRP                   Refresh Prescaler


Data ALU

 A2:A1:A0    	Data ALU Accumulator Register A
 B2:B1:B0    	Data ALU Accumulator Register B
 X1:X0, Y1:Y0	Data ALU Input Register


Address Generation Unit

 R0..R7      	Address Register
 N0..N7      	Offset Register
 M0..M7      	Modulo Register
 EP          	Stack Extension Pointer


Program Control Unit

 PC      	Program Counter Register
 LA      	Loop Address Register
 LC      	Loop Count Register
 EP            Stack Extension Pointer (located in AGU)
 SC      	Stack Count Register
 SZ      	Stack Size Register (SSH, SSL)
 VBA     	Vector Base Address Register

SP       Stack Pointer Register

SR       Status Register

OMR   Operating Mode Register

IPRC   Interrupt Priority Register C

IPRP   Interrupt Priority Register P

 IDR     Device Identification (ID) Register


SP Register
SP Register  Stack Pointer

Program Control Unit

Bit:	Non Extended Mode/Extended Mode
3..0     P3-P0	Stack Pointer
4         SE/P4	Stack Error Flag/Stack Pointer P4
5         UF/P5	Underflow Flag/Stack Pointer P5
23..6   P23-P6	              Stack Pointer P23:P6


SR Register
SR -- Status Register

Program Control Unit

CCR(7:0)	Condition Code Register
Bit:
0     C	Carry
1     V	Overflow
2     Z	Zero
3     N	Negative
4     U  	Unnormalized
5     E 	Extension
6     L 	Limit
7     S 	Scaling Bit

MR(15:8)           Mode Register
9,8     I1,I0           Interrupt Mask bit1:0
11,10   S1,S0      Scaling Mode Bit1:0
12                       Reserved
13      SC            Sixteen Bit Compatibility
14      DM            Double Precision Multiply
15      LF	            DO-Loop Flag

EMR(23:16)	Extended Mode Register

16      FV	DO-Forever Flag
17      SA	Sixteen Bit Arithmetic
18       	Reserved
19      CE	Instruction Cache Enable
20      SM	Arithmetic Saturation
21      RM	Rounding Mode
23,22   CP1,CP0	Core Priority Bit1:0


OMR Register
OMR Operating Mode Register

Program Control Unit

Bits 7-0 COM   Chip Operating Mode

Bit 3-0 MD-MA  Operating Mode D, C, B, A
Bit 4   EBD       External Bus Disable
Bit 5   RESERVED
Bit 6   SD         Stop Delay
Bit 7   MS         Memory Switch Mode

Bits 15-8  EOM Extended Chip Operating Mode

Bit 9-8 CDP1:0  Core-Dma Priority 1, 0
Bit 10  BE         Burst mode Enable
Bit 11  TAS       TA synchronize Select
Bit 12  BRT       BUS Release Timing
Bit 13  ABE      Asyn. Bus Arbitration Enable
Bit 14  APD      Address Priority Disable
Bit 15  ATE      Address Tracing Enable

Bits 23-16  SCS  System Stack Control Status

Bit 16  XYS      Stack Extension Space Select
Bit 17  EUN     Extended Stack Underflow Flag
Bit 18  EOV     Extended Stack Overflow Flag
Bit 19  WRP    Extended Stack Wrap Flag
Bit 20  SEN     Stack Extension Enable
Bit 21  RESERVED
Bit 22  RESERVED
Bit 23  PEN     Patch Enable

RESERVED bits are read as zero,  should be written with zero  for future compatibility

PEN bit description


OMR PEN Bit Description
PEN Bit Description

OMR Register/Patch Enable (PEN) - Bit 23

The Patch Enable function is used for patching Program ROM locations. i.e. to replace during program execution, the contents of the Program ROM. This is done by using the Instruction Cache to supply the instruction word instead of the Program ROM.

The Patch Enable function is activated by setting bit 23 (PEN) in the OMR Register. The PEN bit is cleared by hardware reset.
The Instruction Cache should be initialized with the new instructions according to the following procedure:

These steps should be executed from external memory or by download via host interface:
1. Set Cache Enable = 1
2. Set Patch Enable = 1
3. initialize TAGs to different values by unlock eight different external sectors
4. lock the PATCH sector(s)
5. move new code to locked sector(s), to the addresses that should be replaced
6. start regular PROM program

;-------------------------------------------
; PATCH initialization example
;-------------------------------------------
page 132,55,0,0,0
nolist
INCLUDE "ioequ.asm"
INCLUDE "intequ.asm"
list
START equ $100 ; main program starting address
PATCH_OFSET equ 128 ; patch offset
M_PAE equ 23 ; Patch Enable
M_PROMS equ $ff87ec ; ROM area Start
M_PROME equ $ff87ff ; ROM area End
org P:START
move #M_PROMS,r0
bset #M_CE,sr ; CacheEnable = 1
bset #M_PAE,omr ; PatchEnable = 1
move #$800000,r1 ; any external address
move #128,n1 ; 128 for 1K ICACHE, sector size
move #(M_PROMS+PATCH_OFSET),r2
dup 8
punlock(r1)+n1 ; initialize TAGs to different
; values
endm
plock (r2) ; lock patch's sector
; (start/mid/end)
move #PATCH_DATA_START,r1
;
; replace ROM code by PATCH
;
do #(PATCH_DATA_END-PATCH_DATA_START+1),PATCH_LOOP
movem p:(r1)+,x0
movem x0,p:(r2)+
nop ; Do-loop restriction
PATCH_LOOP
jsr #M_PROMS ; start ROM code execution
ENDTEST jmp ENDTEST
nop
nop
nop
nop
;
; patch data
;
PATCH_DATA_START
move #5,m0
move #6,m1
move #7,m2
PATCH_DATA_END


IPR Register
IPR Registers

Program Control Unit

There are two interrupt priority registers in the DSP56362:
IPR-C is dedicated for DSP56300 Core interrupt sources and
IPR-P is dedicated for DSP56362 peripheral interrupt sources.

IPR-C

Bit 1-0     IAL1-IAL0   IRQA IPL
Bit 2        IAL2          IRQA mode
Bit 4-3     IBL1-IBL0   IRQB IPL
Bit 5        IBL2          IRQB mode
Bit 7-6     ICL1-ICL0   IRQC IPL
Bit 8        ICL2          IRQC mode
Bit 10-9   IDL1-IDL0   IRQD IPL
Bit 11      IDL2          IRQD mode
Bit 13-12 D0L1-D0L0 DMA0 IPL
Bit 15-14 D1L1-D1L0 DMA1 IPL
Bit 17-16 D2L1-D2L0 DMA2 IPL
Bit 19-18 D3L1-D3L0 DMA3 IPL
Bit 21-20 D4L1-D4L0 DMA4 IPL
Bit 23-22 D5L1-D5L0 DMA5 IPL

IPR-P

Bit 1-0   ESL1-ESL0 ESAI IPL
Bit 3-2   SHL1-SHL0 SHI IPL
Bit 5-4   HDL1-HDL0 HDI08 IPL
Bit 7-6   DAL1-DAL0 DAX IPL
Bit 9-8   TAL1-TAL0  TRIPLE TIMER IPL
Bit 23-10  RESERVED, Read as zero, should be zero for future compatibility

Interrupt Priority Level Bits


IPR Interrupt Priority Level Bits

IPL bits         Interrupts Enabled    Interrupt Priority Level
xxL1 xxL0
0      0           No                                        —
0      1          Yes                                        0
1      0          Yes                                        1
1      1          Yes                                        2


IDR Register
IDR  Device Identification Register

Program Control Unit

The Device Identification Register (IDR) is a 24 bit read only factory programmed register used to identify the different DSP56300 core-based family members. This register specifies the derivative number and revision number. This information may be used in testing or by software.
IDR Configuration:

Bits 11-0    Derivative Number  $362
Bits 15-12  Revision Number    $0
Bits 23-16  RESERVED           $00


Topic2
DMA Controller

DMA_DCR(5-0)       DMA Control Register (channel 5-0)

DMA_DSTR             DMA Status Register

DMA_DOR(3-0)       DMA Offset Registers

DMA_DCO(5-0)       DMA Counter    (channel 5-0)

DMA_DSR(5-0)        DMA Source Address Register    (channel 5-0)

DMA_DDR(5-0)        DMA Destination Address Register    (channel 5-0)


Topic1
DMA Register DCR

X:$FFFFEC Read/Write   24-bit Register  DCR0
X:$FFFFE8 Read/Write   24-bit Register   DCR1
X:$FFFFE4 Read/Write   24-bit Register   DCR2
X:$FFFFE0 Read/Write   24-bit Register   DCR3
X:$FFFFDC Read/Write   24-bit Register  DCR4
X:$FFFFD8 Read/Write   24-bit Register   DCR5

Bit:
1,0          DSS1-DSS0	             DMA Source Memory Space
3,2          DDS1-DDS0	             DMA Destination Memory Space
9..4         DAM5-DAM0	              Address Generation Mode
9,8          BPS1-BPS0	              DRAM Page Size
10           D3D	3 & non 3 dimensional modes
15..11     DRS4-DRS0	DMA Request Source
16           DCON	              DMA Continuous Mode
18..17     DPR1-DPR0	DMA Channel Priority
21..19     DTM2-DTM0	DMA Transfer Mode
22           DIE	DMA Interrupt Enable Bit
23           DE	DMA Channel Enable Bit


DSTR Register
DSTR DMA Status Register

X:$FFFFF4 Read/Write   24-bit Register

Bit:
5..0       DTD5-DTD0	DMA Transfer Done Status Bits
6,7       	Reserved
8           DACT	DMA Ac
8,9       BPS1-BPS0	DRAM Page Size
10        D3D	3 & non 3 dimensional medes
15..11 DRS4-DRS0   	DMA Request Source
16        DCON	DMA Continuous Mode
18,17   DPR1-DPR0 	DMA Channel Priority
21..19  DTM2-DTM0 	DMA Transfer Mode
22        DIE	DMA Interrupt Enable Bit
23        DE	DMA Channel Enable Bit


DOR Register
DMA Offset Registers DOR (3-0)

X:$FFFFF3 Read/Write   24-bit Register DOR0
X:$FFFFF2 Read/Write   24-bit Register DOR1
X:$FFFFF1 Read/Write   24-bit Register DOR2
X:$FFFFF0 Read/Write   24-bit Register DOR3

This register contains the offset value to be used in some of the DMA addressing modes. Registers DOR0-DOR3 can be used by all the channels according to their address generation mode.


DCO Register
DMA Counter Registers DCO(5-0)

X:$FFFFED Read/Write   24-bit Register DCO0
X:$FFFFE9 Read/Write   24-bit Register DCO1
X:$FFFFE5 Read/Write   24-bit Register DCO2
X:$FFFFE1 Read/Write   24-bit Register DCO3
X:$FFFFDD Read/Write   24-bit Register DCO4
X:$FFFFD9 Read/Write   24-bit Register DCO5

This register contains the number of DMA data transfers to be done. The DCO has five modes of operations deteermined by the DMA channel's address deneration mode that are defined in the DMA channel's Control Register


DSR Register

X:$FFFFEF Read/Write   24-bit Register DSR0
X:$FFFFEB Read/Write   24-bit Register DSR1
X:$FFFFE7 Read/Write   24-bit Register DSR2
X:$FFFFE3 Read/Write   24-bit Register DSR3
X:$FFFFDF Read/Write   24-bit Register DSR4
X:$FFFFDB Read/Write   24-bit Register DSR5

This register contains the source for the next DMA transfer. The DMA controller has one source address register for each DMA channel.


DDR Register
DMA Destination Address Registers DRR(5-0)

X:$FFFFEF Read/Write   24-bit Register DDR0
X:$FFFFEA Read/Write   24-bit Register DDR1
X:$FFFFE6 Read/Write   24-bit Register DDR2
X:$FFFFE2 Read/Write   24-bit Register DDR3
X:$FFFFDE Read/Write   24-bit Register DDR4
X:$FFFFDA Read/Write   24-bit Register DDR5

This register contains the destination address for the next DMA transfer. The DMA controller has one source address register for each DMA channel.


PLL Clock Oscillator
PLL Clock Oscillator Register PCTL

X:$FFFFFD    24-bit Register

Bit:
11..0      MF11-MF0	Multiplication Factor Bits
14..12    DF2-DF0	Division Factor Bits
15          XTLR	Crystal Range Bit
16          XTLD	Disable Bit
17         PSTP	STOP Processing State Bit
18          PEN	PLL Enable Bit
19          COD	Clock Output Bit
23..20   PD3-PD0	PreDivider Factor Bits


OnCE
OnCE REGISTERS

OSCR            OnCE Status and Control Register

OBCR            OnCE Breakpoint Control Register

 OTAGBSR   OnCE Cache Tag LRU/LOCK Status Register

 OMBC   	    OnCE Memory Breakpoint Counter
 OMLR   	    OnCE Memory Limit Register
 OGDBR       OnCE Global Data Bus Register
 OPDBR       OnCE Program Data Bus Register
 OPILR          OnCE Program Instruction Latch Register
 OTC    	     OnCE Trace Counter
 OTAGB  	     OnCE Cache Tag Register
 OPABFR     OnCE Program Address Bus Register
 OPABDR    OnCE Program Address Bus Decode Register
 OPABEX    OnCE Program Address Bus Execute Register
 OFIFO  	    OnCE Program Address Bus Fifo Register
 OGDB  	    OnCE GDB Register; X:$FFFFFC


OSCR Register
OnCE Status And Control Register OSCR

Bit:
0   	TME     	Trace Mode Enable
1   	IME     	Interrupt Mode Enable
2   	SWO     	Software Debug Occurrence
3   	MBO     	Memory Breakpoint Occurrence
4   	TO      	Trace Occurrence
5   	HIT     	Cache Hit
7,6 	OS1,OS0	Core Status Bits
23..8          	RESERVED;  read as zero and should be written as zero


OBCR Register
OnCE Breakpoint Control Register OBCR

Bit:

1,0    	MBS1,MBS0	Memory Breakpoint Select Bits
3,2    	RW01,RW00	Breakpoint 0 Read/Write Select Bits
5,4    	CC01,CC00	Breakpoint 0 Read/Write Select Bits
7,6    	RW11,RW10	Breakpoint 1 Read/Write Select Bits
9,8    	CC11,CC10	Breakpoint 1 Read/Write Select Bits
11,10  	BT1,BT0   	Breakpoint 0 and 1 Event Select Table
23..12	         	RESERVED; read as zero and should be written as zero


OTAGBSR Register
OnCE Cache Tag LRU/LOCK Status Register OTAGBSR

Bit:
7..0	  0
8   	LOCK7
9   	LRU7 	 	.
.   	.
20  	LOCK1
21  	LRU1
22  	LOCK0
23  	LRU0


JTAG
JTAG Test Access Port

ID Register

BSR Boundary Scan Register


JTAG register ID
ID JTAG Identification Register

The JTAG Identification (ID) Register is a 32 bit, read only throught JTAG, factory programmed register used to distinguish the component on a board according to the IEEE 1149.1 standard.

JTAG ID Configuration
Bit     0            1
Bits 11-1        Manufacturer Identity      00000001110
Bits 21-12      Sequence Number         0001100010
Bits 27-22      Customer Part Number  000110
Bits 31-28      Version Information       0000


JTAG register BSR
BSR

Core

The boundary scan register (BSR) in the DSP56362 JTAG implementation contains bits for all device signal and clock pins and associated control signals. All bidirectional pins have a single register bit in the boundary scan register for pin data, and are controlled by an associated control bit in the boundary scan register.


HDI08
HDI08 Host Interface

Introduction

Diagram

Host Side Registers After Reset

Registers accessible by the host processor:

ICR

CVR

ISR

IVR

RXH/RXM/RXL

TXH/TXM/TXL

Registers accessible by the DSP Core:

HCR

HSR

HDDR

HDR

HBAR

HPCR

HOTX

HORX


HDI08 Introduction

The HDI08 is a byte-wide, full-duplex, double-buffered, parallel port which may be connected directly to the data bus of a host processor. The HDI08 supports a variety of buses, and provides glueless connection with a number of industry standard  microcomputers, microprocessors, DSPs and DMA hardware.

The host bus may operate asynchronously to the DSP Core clock, therefore the HDI08 registers are divided into 2 banks – the 'Host side' bank is accessible to the external host, and the 'DSP side' bank is accessible to the DSP Core.

The HDI08 supports 3 classes of interfaces:
* Host processor/MCU connection interface
* DMA controller interface
* General purpose I/O (GPIO) port

Host port pins not in use may be configured as general purpose I/O pins. The HDI08 provides up to 16 general purpose I/O pins. These pins can be programmed to function as either GPIO or Host Interface.

GENERAL PURPOSE I/O
When configured as general-purpose I/O, the HDI08 is viewed by the DSP Core as  memory-mapped registers  that control up to 16 I/O pins. The software and hardware resets configure HDI08 as general-purpose I/O with all 16 pins disconnected, by clearing all DSP side control registers (external circuitry connected to these pins may need external pull-up/pull-down resistors until the pins are configured for operation). These registers are the
HDI08 port control register (HPCR), the HDI08 data direction register (HDDR), and the HDI08 data register (HDR). Selection between general-purpose I/O and HDI08 is made by clearing HPCR bits 6-1 for general-purpose I/O or setting these bits for HDI08 functionality. The HDDR configures each corresponding pin in the HDR, as an input pin if the HDDR bit is cleared or as an output pin if the HDDR bit is set (see HDDR and HDR).


HDI08 Block Diagram


Host Side Registers After Reset


HDI08 register ICR
ICR  Interface Control Register

HDI08 Host side

The HDI08 register ICR is an 8-bit read/write control register used by the host processor to control the HDI08 interrupts and flags. The ICR cannot be accessed by the DSP Core. The ICR is a read/write register, which allows the use of bit  manipulation instructions on control register bits. The control bits are described in the following paragraphs. The function of the ICR bits is controlled by the HDM2-HDM0 bits of the HCR.

ICR bits for different HDM2-HDM0 values

Bit 0    RREQ  Receive Request Enable

Bit 1    TREQ     Transmit Request Enable

Bit 2    RESERVED for HDM2-DM0 = 100 and non-zero values of HDM1 and HDM0

Bit 2    HDRQ     Double Host Request  only for HDM2-HDM0 = 000

Bit 4-3  F1 HF0  Host Flags

Bit 5     HBEND                                        for HDM2-HDM0= 000

Bit 6     RESERVED                                 for HDM2-HDM0= 000

Bit 6-5 HM1, HM0 for HDM2-HDM0 = 100

Bit 6-5 HDM1, HDM0   for non-zero values of HDM1 and HDM;   Read only bits reflect the value of the HDM1 and HDM0 bits in HCR

Bit 7    INIT        Initialize Bit

See also:

Little Endian and Big Endian

The effect of RREQ and TREQ on the HREQ, HTRQ, and HRRQ pins


ICR register bits for different HDM values
ICR register bits for different HDM2-HDM0 values

HDM2-HDM0=000
Bit 0    RREQ
Bit 1    TREQ
Bit 2    HDRQ
Bit 4-3 HF1-HF0
Bit 5    HBEND
Bit 6    RESERVED
Bit 7    INIT

HDM2-HDM0=100
Bit 0    RREQ
Bit 1    TREQ
Bit 2    RESERVED
Bit 4-3 HF1-HF0
Bit 6-5 HM1-HM0
Bit 7    INIT

non-zero values of HDM1 and HDM0
Bit 0    RREQ
Bit 1    TREQ
Bit 2    RESERVED
Bit 4-3 HF1-HF0
Bit 6-5 HDM1-HDM0  Read only bits reflect the value of the HDM1 and HDM0 bits in HCR
Bit 7    INIT


ICR register bit 0
HDI08 Register: ICR Bit:0 (RREQ)  Receive Request Enable

The RREQ bit is used to control the HREQ and HRREQ pins for host receive data transfers. In interrupt mode (DMA off), RREQ is used to enable host requests via the host request (HREQ or HRRQ) pin when the receive data register full (RXDF) status bit in the ISR is set. If RREQ is cleared, RXDF interrupts are disabled. If RREQ is set, the host request pin (HREQ or HRRQ) will be asserted if RXDF is set.
In DMA modes (HDM2-HDM0 = 100 in the HCR), RREQ must be set or cleared by software to select the direction of DMA transfers. Setting RREQ sets the direction of DMA transfer to be DSP to host and enables the HREQ pin to request data transfer.


ICR register bit 1
HDI08 Register:ICR    Bit: 1  (TREQ) Transmit Request Enable

The TREQ bit is used to control the HREQ/HTREQ pin for host transmit data transfers. In interrupt mode (DMA off), TREQ is used to enable host requests via the host request (HREQ or HTRQ) pin when the transmit data register empty (TXDE) status bit in the ISR is set. If TREQ is cleared, TXDE interrupts are disabled. If TREQ is set, the host request pin will be asserted if TXDE is set.
In DMA modes (HDM2-HDM0 = 100 in the HCR), TREQ must be set or cleared by software to select the direction of DMA transfers. Setting TREQ sets the direction of DMA transfer to be host to DSP and enables the HREQ pin to request data transfer.
See also: The effect of RREQ and TREQ on the HREQ, HTRQ and HRRQ pins.


ICR register bit 2
HDI08 Register ICR  Bit:2 (HDRQ)  Double Host Request

The HDRQ bit is used to control the HREQ/HTRQ and HACK/HRRQ pins. If HDRQ is cleared, the HREQ/HTRQ and HACK/HRRQ pins function as HREQ and HACK respectively. If HDRQ is set, HREQ/HTRQ and HACK/HRRQ pins function as are HTRQ and HRRQ respectively.


ICR register bit 3 and 4
HDI08 Register: ICR  Bit: 3(HF0) and 4 (HF1)  Host Flags

The HFx bit is used as a general-purpose flag for host to DSP communication. HFx may be set or cleared by the host processor and cannot be changed by the DSP Core. HFx is reflected in the HSR on the DSP side of the HDI08. (x=0,1)


ICR register bit 5
HDI08 Register: ICR  Bit:5 (HBEND) Host Big Endian

This bit is available if HDM2-HDM0 = 000 in the host control register (HCR).
If the HBEND bit is cleared, the HDI08 can be accessed by the host in little endian host data order. If set, the HDI08 can be accessed by the host in data order. If the HBEND bit in the ICR is cleared (“Little Endian” order) the RXH/TXH is located at address $6 and RXL/TXL at $7. If the HBEND bit in the ICR is set (“big Endian” order) the RXH/TXH is located at address $7 and RXL/TXL at $6.


ICR register bit 5 and 6 for HDM 100
HDI08 Register: ICR  Bit: 5(HM0) and 6(HM1)   Host Mode Control

These bits are available if HDM2-HDM0 = 100 in the host control register (HCR).
The HM0 and HM1 bits select the transfer mode of the HDI08. HM1 and HM0 enable the DMA mode of operation or interrupt (non-DMA) mode of operation.
HM1/HM0       Mode
       0 0        Interrupt Mode (DMA Off)
       0 1        DMA Mode (24 Bit)
       1 0        DMA Mode (16 Bit)
       1 1         DMA Mode (8 Bit)

When both HM1 and HM0 are cleared, the DMA mode is disabled, and the TREQ and RREQ control bits are used for host processor interrupt control via the external HREQ output pin. Also, in the non-DMA mode, the HACK input pin is used for the MC68000 Family vectored interrupt acknowledge input.
When HM1 or HM0 are set, the DMA mode is enabled, and the HREQ pin is used to request DMA transfers. When the DMA mode is enabled, the TREQ and RREQ bits select the direction of DMA transfers. The HACK input pin is used as a DMA transfer acknowledge input. If the DMA direction is from DSP to host, the contents of the selected register are enabled onto the host data bus when HACK is asserted. If the DMA direction is from host to DSP, the selected register is written from the host data bus when HACK is asserted.
The size of the DMA word to be transferred is determined by the DMA control bits, HM0 and HM1. The HDI08 data register selected during a DMA transfer is determined by a 2-bit address counter, which is preloaded with the value in HM1 and HM0. The address counter substitutes for the HA1 and HA0 bits of the HDI08 during a DMA transfer. The host address bit (HA2) is forced to one during each DMA transfer. The address counter can be initialized with the INIT bit feature.  After each DMA transfer on the host data bus, the address counter is incremented to the next register. When the address counter reaches the highest register (RXL or TXL), the address counter is not incremented but is loaded with the value in HM1 and HM0. This allows 8-, 16- or 24-bit data to be transferred in a circular fashion and eliminates the need for the DMA controller to supply the HA2, HA1, and HA0 pins. For 16- or 24-bit data transfers, the DSP CPU interrupt rate is reduced by a factor of 2 or 3, respectively, from the host request rate – i.e., for every two or three host
processor data transfers of one byte each, there is only one 24-bit DSP CPU interrupt. These bits are available if HDM2-HDM0 = 100 in the host control register (HCR).


ICR register bit 7
HDI08 Register: ICR  Bit:7 (INIT)   Initialize Bit

The INIT bit is used by the host processor to force initialization of the HDI08 hardware. Initialization consists of configuring the HDI08 transmit and receive control bits. Using the INIT bit to initialize the HDI08 hardware may or may not be necessary, depending on the software design of the interface.
The type of initialization done when the INIT bit is set depends on the state of TREQ and RREQ in the HDI08. The INIT command, which is local to the HDI08, is designed to conveniently configure the HDI08 into the desired data transfer mode. The commands are described in table below. The host sets the INIT bit, which causes the HDI08 hardware to execute the INIT command. The interface hardware clears the INIT bit when the command has been executed.

INIT Commands Table

TREQ RREQ        After INIT Execution                 Transfer DIrection Initialized
   0        0                     INIT=0                               None
   0        1            INIT=0; RXDF=0; HTDE=1            DSP to Host
   1        0            INIT=0; TXDE=1; HRDF=0            Host to DSP
   1        1    INIT=0; RXDF=0; HTDE=1; TXDE=1;     HRDF=0 Host to/from DSP


Little and Big Endian


RREQ and TREQ effect
RREQ and TREQ  Bits

TREQ RREQ Interrupt Mode (HM1=HM0=0, HDRQ=0)
TREQ RREQ HREQ Pin
   0        0      No Interrupts (Polling)
   0        1      RXDF Request (Interrupt)
   1        0      TXDE Request (Interrupt)
   1        1      RXDF and TXDE Request (Interrupts)

TREQ RREQ Interrupt Mode (HM1=HM0=0, HDRQ=1)
TREQ RREQ HTRQ Pin HRRQ Pin
  0        0      No Interrupts (Polling) No Interrupts (Polling)
  0        1      No Interrupts (Polling) RXDF Request (Interrupt)
  1        0      TXDE Request (Interrupt) No Interrupts (Polling)
  1        1      TXDE Request (Interrupt) RXDF Request (Interrupt)

TREQ RREQ DMA Mode (HM1not =0 or HM0 not =0)
TREQ RREQ HREQ Pin
  0        0      No DMA
  0        1      DSP to Host Request (RX)
  1        0      Host to DSP Request (TX)
  1        1      Undefined (Illegal)


HDI08 register CVR
CVR  Command Vector Register

HDI08 Host side

The HDI08 register, CVR, is used by the host processor to cause the DSP Core to execute an interrupt. The host command feature is independent of any of the data transfer mechanisms in the HDI08. It can be used to cause any of the 128 possible interrupt routines in the DSP Core to be executed.

Bit 6-0 HV6-HV0    Host Vector

Bit 7    HC            Host Command Bit


CVR register bit 0 to 6
HDI08 Register: CVR  Bit: 6-0 (HV6:0)  Host Vector

The seven HV bits select the host command interrupt address to be used by the host command interrupt logic. When the host command interrupt is recognized by the DSP interrupt control logic, the address of the interrupt routine taken is 2HV. The host can write HC and HV in the same write cycle.
The host processor can select any of the 128 possible interrupt routine starting addresses in the DSP by writing the interrupt routine address divided by 2 into HV. This means that the host processor can force any of the existing interrupt handlers (SSI, SCI, IRQA, IRQB, etc.) and can use any of the reserved or otherwise unused addresses provided they have been pre-programmed in the DSP.


CVR register bit 7
HDI08 Register: CVR  Bit: 7 (HC)  Host Command Bit

The HC bit is used by the host processor to handshake the execution of host command interrupts. Normally, the host processor sets HC=1 to request the host command interrupt from the DSP Core. When the host command interrupt is acknowledged by the DSP Core, the HC bit is cleared by the HDI08 hardware. The host processor can read the state of HC to determine when the host command has been accepted. After writing HC=1 to the CVR, the host must not write to the CVR again until HC is cleared by the HDI08 hardware. Setting HC causes host command pending (HCP) to be set in the HSR. The host can write HC and HV in the same write cycle if desired.


HDI08 register ISR
ISR Interface Status Register

HDI08 Host side

The ISR is an 8-bit read-only status register used by the host processor to interrogate the status and flags of the HDI08. The host processor can write this address without affecting the internal state of the HDI08, which is useful if the user desires to access all of the HDI08 registers by stepping through the HDI08 addresses. The ISR can not be accessed by the DSP Core. The status bits are
described in the following paragraphs.

Bit 0    RXDF        Receive Data Register Full

Bit 1    TXDE        Transmit Data Register Empty

Bit 2    TRDY       Transmitter Ready

Bit 4-3 HF3-HF2   Host Flag 3 and 2 (see also HCR register)

Bit 6-5                 RESERVED, Read as 0. Should be written with 0, for future compatibility

Bit 7    HREQ       Host Request


ISR register bit 0
HDI08 Register: ISR  Bit 0 (RXDH)  Receive Data Register Full

The RXDF bit indicates that the receive byte registers (RXH, and RXL) contain data from the DSP Core and may be read by the host processor. RXDF is set when the HOTX is transferred to the receive byte registers. RXDF is cleared when the receive data (RXL or RXH according to HBEND bit) register is read by the host processor. RXDF can be cleared by the host processor using the initialize function. RXDF may be used to assert the external HREQ pin if the RREQ bit is set. Regardless of whether the RXDF interrupt is enabled, RXDF provides valid status so that polling techniques may be used by the host processor.


ISR register bit 1
HDI08 Register: ISR  Bit 1 (TXDE)  Transmit Data Register Empty

The TXDE bit indicates that the transmit byte registers (TXH, and TXL) are empty and can be written by the host processor. TXDE is set when the transmit byte registers are transferred to the HORX register. TXDE is cleared when the transmit (TXL or TXH according to HBEND bit) register is written by the host processor. TXDE can be set by the host processor using the initialize feature. TXDE may be used to assert the external HREQ pin if the TREQ bit is set. Regardless of whether the TXDE interrupt is enabled, TXDE provides valid status so that polling techniques may be used by the host processor.


ISR register bit 2

HDI08 Register: ISR  Bit:2 (TRDY) Transmitter Ready

The TRDY status bit indicates that TXH, TXL and the HORX registers are empty.
TRDY=TXDE · !  HRDF
If TRDY is set to 1, the data that the host processor writes to TXH, and TXL will be immediately transferred to the DSP side of the HDI08. This has many applications. For example, if the host processor issues a host command which causes the DSP Core to read the HORX, the host processor can be guaranteed that the data it just transferred to the HDI08 is what is being received by the DSP Core.


ISR register bit 3 and 4
HDI08 Register: ISR  Bit: 3 and 4 (HF2 and HF3) Host Flags

Host Flag 2 (HF2) Bit 3 in the ISR indicates the state of host flag 2 in the HCR on the DSP side. HF2 can only be changed by the DSP (see HCR register).
Host Flag 3 (HF3) Bit 4 in the ISR indicates the state of host flag 3 in the HCR on the DSP side. HF3 can only be changed by the DSP (see  HCR register).


ISR register bit 7
HDI08 Register: ISR  Bit 7 (HREQ) Host Request

The HREQ bit indicates the status of the external host request output pin (HREQ) if HDRQ is cleared; or the external transmit and receive request output pins (HTRQ and HRRQ respectively) if HDRQ is set.
If HDRQ is cleared: If the HREQ status bit is cleared, it indicates that the host request pin (HREQ) is negated and no host processor interrupts are being requested. If the HREQ status bit is set, it indicates that

 The host request pin (HREQ) is asserted, indicating that the DSP is interrupting the host processor.

If HDRQ is set: If the HREQ status bit is cleared, it indicates that the HTRQ and HRRQ pins are negated and no host processor interrupts are being requested. When the HREQ status bit is set, it indicates that

 The HTRQ pin or HRRQ pin is asserted, indicating that the DSP is interrupting the host processor.

The HREQ bit may be set from either or both of two sources – the receive byte registers are full or the transmit byte registers are empty. These conditions are indicated by the ISR RXDF and TXDE status bits, respectively. If the interrupt source has been enabled by the associated request enable bit in the ICR, HREQ will be set if one or more of the two enabled interrupt sources is set.


HDI08 register IVR
IVR Interrupt Vector Register

HDI08 Host side

The IVR is an 8-bit read/write register which typically contains the interrupt vector number used with MC68000 Family processor vectored interrupts. Only the host processor can read and write this register. The contents of IVR are placed on the host data bus (H0–H7) when both the HREQ and HACK pins are asserted. The contents of this register are initialized to $0F by a hardware or software reset, which corresponds to the uninitialized interrupt vector in the MC68000 Family.

Bit 7-0 IV7-IV0


HDI08 register RXH RXM RXL
RXH/RXM/RXL  Receive Byte Registers

HDI08 Host side

The receive byte registers are viewed as three 8-bit read-only registers by the host processor. These registers are called receive high (RXH), receive middle (RXM) and receive low (RXL). These registers receive data from the high, middle and low bytes, respectively, of the HOTX register and are selected by the external host address inputs (HA2, HA1 and HA0) during a host processor read
operation. The receive byte registers (at least the data register at host address $7) contain valid data when the receive data register full (RXDF) bit is set. The host processor may program the RREQ bit to assert the external HREQ pin when RXDF is set. This informs the host processor that the receive byte registers are full. Reading the data register at host address $7 clears the RXDF bit. If
the HBEND bit in the ICR is cleared, the RXH is located at address $5, RXM at $6 and RXL at $7. If the HBEND bit in the ICR is set, the RXH is located at address $7, RXM at $6 and RXL at $5.


HDI08 register TXH TXM TXL
TXH/TXM/TXL Transmit Byte Registers

HDI08 Host side

The transmit byte registers are viewed as three 8-bit write-only registers by the host processor. These registers are called transmit high (TXH), transmit middle (TXM) and transmit low (TXL). These registers send data to the high, middle and low bytes, respectively, of the HORX register and are selected by the external host address inputs (HA2, HA1 and HA0) during a host processor write operation. Data may be written into the transmit byte registers when the transmit data register empty (TXDE) bit is set. The host processor may program the TREQ bit to assert the external HREQ pin when TXDE is set. This informs the host processor that the transmit byte registers are empty. Writing the data register at host address $7 clears the TXDE bit. If the HBEND bit in the ICR is cleared, the TXH is located at address $5, TXM at $6 and TXL at $7. If the HBEND bit in the ICR is set, the TXH is located at address $7, TXM at $6 and TXL at $5. The transmit byte registers are transferred as 24-bit data to the HORX register when both TXDE and the HRDF bit are cleared. This transfer operation sets TXDE and HRDF.


HDI08 register HCR
HCR        Host Control Register

HDI08 DSP Side

Bits:

0          HRIE     Host Receive Interrupt Enable

1          HTIE     Host Transmit Interrupt Enable

2          HCIE     Host Command Interrupt Enable

4, 3      HF3-2    Host Flags 2,3

7-5       HDM2-0 Host DMA Mode Control Bits

15 - 8    RESERVED. Read as 0. Should be written with 0 for future compatibility


HCR register bit 0

Host Receive Interrupt Enable (HRIE)
The HRIE bit is used to enable a DSP Core interrupt when the host receive data full (HRDF) status bit in the host status register (HSR) is set. If HRIE is cleared, HRDF interrupts are disabled. If HRIE is set, a host receive data interrupt request will occur if  RDF is set.


HCR register bit 1

Host Transmit Interrupt Enable (HTIE)
The HTIE bit is used to enable a DSP Core interrupt when the host transmit data empty (HTDE) status bit in the HSR is set. If HTIE is cleared, HTDE interrupts are disabled. If HTIE is set, a host transmit data interrupt request will occur if HTDE is set.


HCR register bit 2

Host Command Interrupt Enable (HCIE)
The HCIE bit is used to enable a DSP Core interrupt when the host command pending (HCP) status bit in the HSR is set. If HCIE is cleared, HCP interrupts are disabled. If HCIE is set, a host command interrupt request will occur if HCP is set. The interrupt address is determined by the host command vector register (CVR).

NOTE: Host interrupt request priorities: If more than one interrupt request source is asserted and enabled(e.g. HRDF=1, HCP=1, HRIE=1 and HCIE=1), the HDI08 will generate interrupt requests according to the following table:

Priority        Interrupt Source
Highest        Host Command (HCP=1)
                   Transmit Data (HTDE=1)
Lowest         Receive Data (HRDF=1)


HCR register bits 3 and 4

Host Flags 2,3 (HF2,HF3)
HF2 and HF3 bits are used as a general-purpose flags for DSP to host communication. HF2 and HF3 may be set or cleared by the DSP Core. HF2 and HF3 are reflected in the interface status register (ISR) on the host side such that if they are modified by the DSP software, the host processor can read the modified values by reading the ISR. These two flags are not designated for any specific purpose but are general-purpose flags. They can be used  ndividually or as encoded pairs in a simple DSP to host ommunication protocol, implemented in both the DSP and the host processor software.


HCR register bits 5 to 7

Host DMA Mode Control Bits (HDM0, HDM1, HDM2)
The HDM2-0 bits are used to enable the HDI08 DMA mode operation. The HDI08 DMA mode supports external DMA controller devices connected to the HDI08 on the Host side. This mode should not be confused with the operation of the on-chip DMA controller. With HDM2-HDM0 cleared, the HDI08 does not support DMA mode operation and the TREQ and RREQ control bits are used for host processor interrupt control via the external HREQ output pin
(or HRREQ and HTREQ output pins if HDREQ in the ICR is set). Also, in the non-DMA mode, the HACK input pin is used for the MC68000 Family vectored interrupt acknowledge input. If HDM2-HDM0 are not all cleared, the HDI08 will operate as described in HCRModeBits.


HDI08 register HSR
HSR Host Status Register

HDI08 DSPside

Bits:5 - 8    RESERVED . Read as 0. Should be written with 0 for future compatibility

Bit  0          HRDF      Host Receive Data Full

Bit 1           HTDE      Host Transmit Data Empty

Bit 2           HCP        Host Command Pending

Bits 3-4     HF1-0      Host Flags 0,1

Bit 7          DMA        HSR DMA Status


HSR register  bit 0

Bit 0         Host Receive Data Full (HRDF)
The HRDF bit indicates that the host receive data register (HORX) contains data from the host processor. HRDF is set when data is transferred from the  XH:TXM:TXL registers to the HORX register. HRDF is cleared when HORX is read by the DSP Core. If HRDF is set the HDI08 generates a receive data full DMA request, if enabled by a DSP Core DMA Channel. If HRDF is set when HRIE is set, a host receive data interrupt request is generated. HRDF can also be  leared by the host processor using the initialize function.


HSR register bit 1

Bit 1         Host Transmit Data Empty (HTDE)
The HTDE bit indicates that the host transmit data register (HOTX) is empty and can be written by the DSP Core. HTDE is set when the HOTX register is transferred to the RXH:RXM:RXL registers. HTDE is cleared when HOTX is written by the DSP Core. If HTDE is set the HDI08 generates a transmit data full DMA request, if enabled by a DSP Core DMA Channel. If HTDE is set when HTIE is set, a host transmit data interrupt request is generated. HTDE can also be set by the host processor using the initialize function.


HSR register bit 2

Bit 2        Host Command Pending (HCP)
The HCP bit indicates that the host has set the HC bit and that a host command interrupt is pending. The HCP bit reflects the status of the HC bit in the command vector register (CVR). HC and HCP are cleared by the HDI08 hardware when the interrupt request is serviced by the DSP Core. The host can clear HC, which also clears HCP.


HSR register bits 3 and 4

Bits 3-4   Host Flags 0,1 (HF0,HF1)
HF0 and HF1 bits are used as a general-purpose flags for host to DSP communication. HF0 and HF1 may be set or cleared by the host. HF0 and HF1 reflect the status of host flags HF0 and HF1 in the ICR register on the host side. These two flags are not designated for any specific purpose but are general-purpose flags. They can be used  individually or as encoded pairs in a simple host to DSP communication protocol, implemented in both the DSP and the host Processor software.


HSR register bit 7

Bit 7       HSR DMA Status (DMA)
The DMA bit, when set, indicates that the DMA mode of operation has been enabled. The following cases may occur (see HCRModeBits:)
a) HDM[2:0] = 100 and the host processor has enabled the DMA mode by setting HM1 or HM0 in the ICR to one, or
b) the DMA mode has been enabled by setting HDM1 or HDM0 in the HCR register to one.
When the DMA bit is zero, it indicates that the DMA mode is disabled. The channel not in use can be used for polled or interrupt operation by the DSP.


HDI08 register HDDR and HDR
HDDR Data Direction Register

HDR   Host Data Register

HDI08 DSP Side

The HDDR controls the direction of each of the HDI08 pins configured as GPIO. Note that even when the HDI08 is used as the host interface, some of its pins may be configured as GPIO pins and the direction of these pins is controlled by this register (for full information regarding all the configuration options, see General Purpose I/O). If bit DRxx is set, the corresponding HDI08 pin is configured as an output pin. If bit is DRxx cleared, the corresponding HDI08 pin is configured as an input pin.
Bit 0-15  DR0-DR15

The HDR register holds the data value of the corresponding bits of the HDI08 pins which are configured as GPIO pins. The bit Dxx functionality depends on the corresponding HDDR bit (DRxx).The HDR cannot be accessed by the host processor.
Bit 0-15  D0-D15

See also:

See HDR and HDDR Functionality.


HDI08 functionality  of HDR and HDDR
HDR and HDDR Functionality

HDI08 DSP Side

For:HDDR/DRxx=0  and HDR/Dxx/GPIO pin
Read only bit. The value read is the binary value of the pin. The corresponding pin is configured as an input.

For:HDDR/DRxx=0  and HDR/Dxx/non-GPIO pin
Read only bit. Does not contain significant data.

For:HDDR/DRxx=1  and HDR/Dxx/GPIO pin
Read/write bit. The value written is the value read. The corresponding pin is configured as an output, and is driven with the data written to Dxx.

For:HDDR/DRxx=1  and HDR/Dxx/non-GPIO pin
Read/write bit. The value written is the value read.

Note: dGPIO pin, non GPIO pin defined by the selected configuration


HDI08 register HBAR
HBAR Host Base Address Register

HDI08 DSP side

The Host Base Address Register is used in multiplexed bus modes. This register selects the base address for the host side registers. The address from the host is compared with the base address as programmed in the base address register, and the internal chip select will be generated if a match is found.

Bit 0-7     BA3-BA10
Bit 8-15   RESERVED, Read as 0. Should be written with 0, for future compatibility.

The mechanism which uses this register is described in:

Self Chip Select Logic.


Self Chip Select Logic


HDI08 register HPCR
HPCR Host Port Control Register

HDI08 DSP side

The HPCR is 16-bit read/write control register used by the DSP to control the HDI08 operating mode. Reserved bits are read as zeros and should be written with zeros for future compatibility. The initialization values for the HPCR bits are described in:  DSP Side Registers after Reset.


HDI08 register HOTX
HOTX Host Transmit Data Register

HDI08 DSP side

The HOTX register is used for DSP to host data transfers. The HOTX register is viewed as a 24-bit write-only register by the DSP Core. Writing the HOTX register clears HTDE. The DSP may program the HTIE bit to cause a host transmit data interrupt when HTDE is set. Also, a DMA Channel may be programmed to write to HOTX when HTDE is set. The HOTX register is transferred as 24-bit data to the receive byte registers (RXH:RXM:RXL) if both the HTDE bit (DSP side) and receive data full (RXDF) status bits (host side) are cleared. This transfer operation sets RXDF and HTDE. Data should not be written to the HOTX until HTDE is set to prevent the previous data from being overwritten.


HDI08 register HORX
HORX Host Receive Data Register

HDI08 DSP side

The HORX register is used for host to DSP data transfers. The HORX register is viewed as a 24-bit read-only register by the DSP Core. The HORX register is loaded with 24-bit data from the transmit data registers (TXH:TXM:TXL) on the host side when both the transmit data register empty TXDE (host side) and DSP host receive data full (HRDF) bits are cleared. This transfer operation sets TXDE and HRDF. The HORX register contains valid data when the HRDF bit is
set. Reading HORX clears HRDF. The DSP may program the HRIE bit to cause a host receive data interrupt when HRDF is set. Also, a DMA channel may be programmed to read the HORX when HRDF is set.


SHI
SHI Serial Port Interface

INTRODUCTION

SERIAL HOST INTERFACE INTERNAL ARCHITECTURE

SHI CLOCK GENERATOR

SERIAL HOST INTERFACE REGISTERS


SHI Introduction

The Serial Host Interface (SHI) is a serial I/O interface that provides a path for communication and program/coefficient data transfers between the DSP and an external host processor. The SHI can also communicate with other serial peripheral devices. The SHI can interface directly to either of two well-known and widely used synchronous serial buses: the Motorola Serial Peripheral Interface (SPI) bus and the Philips Inter-Integrated-circuit Control (I 2 C) bus. The SHI supports either the SPI or I 2 C bus protocol, as required, from a slave or a single-master device. To minimize DSP overhead, the SHI supports single-, double-, and triple-byte data transfers. The SHI has a 10-word receive FIFO that permits receiving up to 30 bytes before generating a receive interrupt, reducing the overhead for data reception.

When configured in the SPI mode, the SHI can:
 Identify its slave selection (in Slave mode)
 Simultaneously transmit (shift out) and receive (shift in) serial data
 Directly operate with 8-, 16- and 24-bit words
 Generate vectored interrupts, separately for receive and transmit events, and update status bits
 Generate a separate vectored interrupt in the event of a receive exception
 Generate a separate vectored interrupt in the event of a bus-error exception
 Optionally trigger DMA interrupts to service the transmit and receive events
 Generate the serial clock signal (in Master mode)

When configured in the I 2 C mode, the SHI can:
 Detect/generate start and stop events
 Identify its slave (ID) address (in Slave mode)
 Identify the transfer direction (receive/transmit)
 Transfer data byte-wise according to the SCL clock line
 Generate ACK signal following a byte receive
 Inspect ACK signal following a byte transmit
 Directly operate with 8-, 16- and 24-bit words
 Generate vectored interrupts separately for receive and transmit events and update status bits
 Generate a separate vectored interrupt in the event of a receive exception
 Generate a separate vectored interrupt in the event of a bus error exception
 Optionally trigger DMA interrupts to service the transmit and receive events
 Generate the clock signal (in Master mode)


SHI Internal Architecture

The DSP views the SHI as a memory-mapped peripheral in the X data memory space. The DSP may access the SHI as a normal memory-mapped peripheral using standard polling or interrupt programming techniques and DMA transfers. Memory mapping allows DSP communication with the SHI registers to be accomplished using standard instructions and addressing modes. In addition, the MOVEP instruction allows interface-to-memory and  emory-to-interface data transfers without going through an intermediate register. The DMA controller may be used to service the receive or transmit data path. The single master configuration allows the DSP to directly connect to dumb peripheral devices. For that purpose, a programmable baud-rate generator is included to generate the clock signal for serial transfers. The host side invokes the SHI, for communication and data transfer with the DSP, through a shift register that may be accessed serially using either the I 2 C or the SPI bus protocols.
See also:

SHI Block diagram


SHI Block Diagram


SHI Clock Generator

The SHI clock generator generates the serial clock to the SHI if the interface operates in the Master mode. The clock generator is disabled if the interface operates in the Slave mode, except in I 2 C mode when the HCKFR bit is set in the HCKR register. When the SHI operates in the Slave mode, the clock is external and is input to the SHI (HMST = 0). Figure below  illustrates the internal clock path connections. It is the user's responsibility to select the proper clock rate within the range as defined in the I 2 C and SPI bus specifications.


SHI Registers

DSP Side

HSAR

HCKR

HCSR

HRX  Receive Data FIFO        X:$FFFF94 SHI DSP Side read only

HTX  Transmit Data Register  X:$FFFF93 SHI DSP Side write only

Host Side

IOSR


SHI register HSAR
HSAR SHI I2C Slave Address Register

SHI, DSP Side                                                                     X: $FFF2

The  24-bit Slave Address Register (HSAR) is used when the SHI operates in the I 2C Slave mode and is ignored in the other operational modes. HSAR holds five bits of the 7-bit slave address of the device. The SHI also acknowledges the general call address (all 0s, 7-bit address, and a 0 R/W bit) specified by the I 2 C protocol, but will treat any following data bytes as regular data, i.e. the SHI does not differentiate between its dedicated address and the general call address. HSAR cannot be accessed by the host processor.

Bit 19, 17-0      RESERVED, read as 0,should be written with 0 for further compatibility
Bit 23-20, 18    HA6-HA3, HA1 Slave Address


SHI register HCKR
HCKR Clock Control Register

SHI, DSP Side                                                         X: $FFF0

The SHI Clock Control Register (HCKR) is a 24-bit read/write register that controls the SHI clock generator operation. The HCKR bits should be modified only while the SHI is in the individual reset state (HEN = 0 in the HCSR).

Note: The programmer should not use the combination HRS = 1 and HDM[7:0] = 00000000, since it may cause synchronization problems and improper operation (it is therefore considered an illegal combination).
Note: The HCKR bits are cleared during hardware reset or software reset, except for CPHA, which is set. The HCKR is not affected by the Stop state.

Bit 0           CPHA          Clock  Phase

Bit 1           CPOL           Clock  Polarity

Bit 2           HRS             Prescaler Rate Select

Bit 10-3      HDM7-0        Divider Modulus Select

Bit 13-12    HFM1-HFM0  Filter Mode

Bit 23-14,11    RESERVED, read as 0,should be written with 0 for further compatibility

For details see also:

SHI Data-to-Clock Timing Diagram

SHI Data-toClock Timing Diagram Description

SHI Noice Reduction Filter Mode Table


HCKR register bits 0 and 1

Clock Phase and Polarity (CPHA and CPOL)
The programmer may select any of four combinations of Serial Clock (SCK) phase and polarity when operating in the SPI mode (refer to: SPI Data-to-Clock Timing Diagram and description). The clock polarity is determined by the Clock Polarity (CPOL) control bit, which selects an active-high or active-low clock. When CPOL is cleared, it produces a steady-state low value at the SCK pin of the master device whenever data is not being transferred. If the CPOL bit is set, a high value is produced at the SCK pin of the master device whenever data is not being transferred.


HCKR register bit 2

HCKR Prescaler Rate Select (HRS)—Bit 2
The HRS bit controls a prescaler in series with the clock generator divider. This bit is used to extend the range of the divider when slower clock rates are desired. When HRS is set, the prescaler is bypassed. When HRS is cleared, the fixed divide-by-eight prescaler is operational. HRS is ignored when the SHI operates in the Slave mode, except for I 2 C when HCKFR is set. The HRS bit is cleared during hardware reset and software reset.

Note: Use the equations in the SHI datasheet to determine the value of HRS for the specific serial clock frequency required.


HCKR register bits 10 to 3

HCKR Divider Modulus Select (HDM[7:0])
The HDM[7:0] bits specify the divide ratio of the clock generator divider. A divide ratio between 1 and 256 (HDM[7:0] = 0 to $FF) may be selected. When the SHI operates in the Slave mode [except for I 2 C when HCKFR is set], the HDM[7:0] bits are ignored. The HDM[7:0] bits are cleared during hardware reset and software reset.

Note: Use the equations in the SHI datasheet to determine the value of HDM[7:0] for the specific serial clock frequency required.


HCKR register bits 13 and 12

HCKR Filter Mode (HFM[1:0])
The read/write control bits HFM[1:0] specify the operational mode of the noise reduction filters(see SHI Noice Reduction Filter Table). The filters are designed to eliminate undesired spikes that might occur on the clock and data-in lines and allow the SHI to operate in noisy environments when required. One filter is located in the input path of the SCK/SCL line and the other is located in the input path of the data line (i.e., the SDA line when in I 2 C mode, the MISO line when in SPI Master mode, and the MOSI line when in SPI Slave mode).


SHI_Timing  Diagram
SPI Data-to-Clock Timing Diagram


SHI Timing Diagram Description

The Clock Phase (CPHA) bit controls the relationship between the data on the MISO and MOSI pins and the clock produced or received at the SCK pin. This control bit is used in conjunction with the CPOL bit to select the desired clock-to-data relationship. The CPHA bit, in general, selects the
clock edge that captures data and allows it to change states. It has its greatest impact on the first bit transmitted (MSB) in that it does or does not allow a clock transition before the data capture edge.

When in Slave mode and CPHA = 0, the SS line must be deasserted and asserted by the external master between each successive word transfer. SS must remain asserted between successive bytes within a word. The DSP core should write the next data word to HTX when HTDE = 1, clearing
HTDE. However, the data will be transferred to the shift register for transmission only when SS is deasserted. HTDE is set when the data is transferred from HTX to the shift register.

When in Slave mode and CPHA = 1, the SS line may remain asserted between successive word transfers. The SS must remain asserted between successive bytes within a word. The DSP core should write the next data word to HTX when HTDE = 1, clearing HTDE. The HTX data will be
transferred to the shift register for transmission as soon as the shift register is empty. HTDE is set when the data is transferred from HTX to the shift register.

When in Master mode and CPHA = 0, the DSP core should write the next data word to HTX when HTDE = 1, clearing HTDE; the data is transferred immediately to the shift register for transmission. HTDE is set only at the end of the data word transmission.
Note: The master is responsible for deasserting and asserting the slave device SS line between word transmissions.

When in Master mode and CPHA = 1, the DSP core should write the next data word to HTX when HTDE = 1, clearing HTDE. The HTX data will be transferred to the shift register for transmission as soon as the shift register is empty. HTDE is set when the data is transferred from HTX to the
shift register.

The clock phase and polarity should be identical for both the master and slave SPI devices. CPHA and CPOL are functional only when the SHI operates in the SPI mode, and are ignored in the I 2 C mode. The CPHA bit is set and the CPOL bit is cleared during hardware reset and software reset.


SHI Noise Reduction Table
SHI Noise Reduction Filter Mode Table

HFM1    HFM0     Description
    0           0          Bypassed (Disabled)
    0           1          Reserved
    1           0          Narrow Spike Tolerance
    1          1           Wide Spike Tolerance

When HFM[1:0] are cleared, the filter is bypassed (spikes are not filtered out). This mode is useful when higher bit-rate transfers are required and the SHI operates in a noise-free environment.

When HFM1 = 1 and HFM0 = 0, the narrow-spike-tolerance filter mode is selected. In this mode the filters eliminate spikes with durations of up to 50ns. This mode is suitable for use in mildly noisy environments and imposes some limitations on the maximum achievable bit-rate transfer.

When HFM1 = 1 and HFM0 = 1, the wide-spike-tolerance filter mode is selected. In this mode the filters eliminate spikes up to 100 ns. This mode is recommended for use in noisy environments; the bit-rate transfer is strictly limited. The wide-spike- tolerance filter mode is highly recommended for use in I 2 C bus systems as it fully conforms to the I 2 C bus specification and improves noise
immunity.

Note: HFM[1:0] are cleared during hardware reset and software reset.

After changing the filter bits in the HCKR to a non-bypass mode (HFM[1:0] not equal to '00'), the programmer should wait at least ten times the tolerable spike width before enabling the SHI (setting the HEN bit in the HCSR). Similarly, after changing the I 2 C bit in the HCSR or the CPOL bit in the HCKR, while the filter mode bits are in a non-bypass mode (HFM[1:0] not equal to '00'), the programmer should wait at least ten times the tolerable spike width before enabling the SHI (setting HEN in the HCSR).


SHI register HCSR
HCSR Control/Status Register

SHI DSP Side                                                                     X:$FFFF90

The HCSR is a 24-bit read/write register that controls the SHI operation and reflects its status. Each bit is described in one of the following paragraphs. When in the Stop state or during individual reset, the HCSR status bits are reset to their hardware-reset state, while the control bits are not affected.

Bit 0           HEN          Host Enable

Bit 1           HI2C          I2C/SPI Selection

Bit 3-2        HM[1-0]      SHI Mode

Bit 4           HCKFR      I2C Clock Freeze

Bit 5           HFIFO       FIFO-Enable

Bit 6           HMST        Master Mode

Bit 8-7        HRQE[1-0] Host-Request Enable

Bit 9           HIDLE       HCSR Idle

Bit 10         HBIE         HCSR Bus-Error Interrupt Enable

Bit 11         HTIE          HCSR Transmit-Interrupt Enable

Bit 13-12    HRIE[1-0]   HCSR Receive Interrupt Enable

Bit 14         HTUE        HCSR Host Transmit Underrun Error

Bit 15         HTDE        HCSR Host Transmit Data Empty

Bit 17         HRNE        Host Receive FIFO Not Empty

Bit 19         HRFF        Host Receive FIFO Full

Bit 20         HROE       Host Receive Overrun Error

Bit 21         HBER       Host Bus Error

Bit 22         HBUSY     HCSR Host Busy

Bit 23,18, 16     RESERVED, read as 0,should be written with 0 for further compatibility

For details see also:

SPI BUS

I2C BUS

HCSR Receive Interrupt Enable Bits Table

SPI Data-to-Clock Timing Diagram


HCSR register bit 0

HCSR Host Enable (HEN)
The read/write control bit Host Enable (HEN) enables the overall operation of the SHI. When HEN is set, SHI operation is enabled. When HEN is cleared, the SHI is disabled (individual reset state, see below). The HCKR and the HCSR control bits are not affected when HEN is cleared. When operating in Master mode, HEN should be cleared only after the SHI is idle (HBUSY = 0). HEN is cleared during hardware reset and software reset.

SHI Individual Reset
While the SHI is in the individual reset state, SHI input pins are inhibited, output and bidirectional pins are disabled (high impedance), the HCSR status bits and the transmit/receive paths are reset to the same state produced by hardware reset or software reset. The individual reset state is entered following a one-instruction-cycle delay after clearing HEN.


HCSR register bit 1

HCSR I 2 C/SPI Selection (HI2C)
The read/write control bit HI2C selects whether the SHI operates in the I2C or SPI modes. When HI2C is cleared, the SHI operates in the SPI mode. When HI2C is set, the SHI operates in the I2C mode. HI2C affects the functionality of the SHI pins. It is recommended that an SHI individual reset be generated (HEN cleared) before changing HI2C. HI2C is cleared during hardware reset and software reset.


HCSR register bits 3 to 2

HCSR Serial Host Interface Mode (HM[1:0])
The read/write control bits HM[1:0] select the size of the data words to be transferred, as shown in table below. HM[1:0] should be modified only when the SHI is idle (HBUSY = 0). HM[1:0] are cleared during hardware reset and software reset.

HM1 HMO Description
0      0       8-bit data
0      1      16-bit data
1      0      24-bit data
1      1      Reserved


HCSR register bit 4

HCSR I 2 C Clock Freeze (HCKFR)
The read/write control bit HCSR I2C Clock Freeze (HCKFR) determines the behavior of the SHI when operating in the I 2 C Slave mode in cases where the SHI is unable to service the master request. The HCKFR bit is used only when operating in the I 2 C Slave mode; it is ignored otherwise.
If HCKFR is set, the SHI will hold the clock line to GND if it is not ready to send data to the master during a read transfer, or if the input FIFO is full when the master attempts to execute a write transfer. In this way, the master may detect that the slave is not ready for the requested transfer, without causing an error condition in the slave. When HCKFR is set for transmit sessions, the SHI
clock generator must be programmed as if to generate the same serial clock as produced by the external master, otherwise erroneous operation may result. The programmed frequency should be equal to or up to 25% less than the external clock frequency.
If HCKFR is cleared, any attempt from the master to execute a transfer when the slave is not ready will result in an overrun or underrun error condition.
It is recommended that an SHI individual reset be generated (HEN cleared) before changingHCKFR.
HCKFR is cleared during hardware reset and software reset.


HCSR register bit 5

HCSR FIFO-Enable Control (HFIFO)
The read/write control bit HCSR FIFO-enable control (HFIFO) selects the size of the receive FIFO. When HFIFO is cleared, the FIFO has a single level. When HFIFO is set, the FIFO has 10 levels. It is recommended that an SHI individual reset be generated (HEN cleared) before changing HFIFO.
HFIFO is cleared during hardware reset and software reset.


HCSR register bit 6

HCSR Master Mode (HMST)
The read/write control bit HCSR Master (HMST) determines the operating mode of the SHI. If HMST is set, the interface operates in the Master mode. If HMST is cleared, the interface operates in the Slave mode. The SHI supports a single-master configuration, in both I 2 C and SPI modes.
When configured as an SPI Master, the SHI drives the SCK line and controls the direction of the data lines MOSI and MISO. The SS line must be held deasserted in the SPI Master mode; if the SS line is asserted when the SHI is in SPI Master mode, a bus error will be generated (the HCSR HBER bit will be set—see Host Bus Error (HBER)—Bit 21).
When configured as an I2C Master, the SHI controls the I2C bus by generating start events, clock pulses, and stop events for transmission and reception of serial data. It is recommended that an SHI individual reset be generated (HEN cleared) before changing HMST. HMST is cleared during hardware reset and software reset.


HCSR register bits 8 and 7

Host-Request Enable (HRQE[1:0])
The read/write Host-Request Enable control bits (HRQE[1:0]) are used to enable the operation of the !HREQ pin. When HRQE[1:0] are cleared, the !HREQ pin is disabled and held in the high impedance state. If either HRQE0 or HRQE1 are set and the SHI is operating in a Master mode, the !HREQ pin becomes an input that controls SCK: deasserting !HREQ will suspend SCK. If either HRQE0 or HRQE1 are set and the SHI is operating in a Slave mode, !HREQ becomes an output and its operation is defined in Table below. HRQE[1:0] should be modified only when the SHI is idle (HBUSY = 0).
HRQE[1:0] are cleared during hardware reset and software reset.

HREQ Function In SHI Slave Modes Table

HRQE1   HRQE0       HREQ pin Operation
     0            0              High impedance
     0            1              Asserted if IOSR is ready to receive a new word
     1            0              Asserted if IOSR is ready to transmit a new word
     1            1              I2C: Asserted if IOSR is ready to transmit or receive
                                  SPI: Asserted if IOSR is ready to transmit and receive


HCSR register bit 9

HCSR Idle (HIDLE)
The read/write control/status bit Host Idle (HIDLE) is used only in the I 2 C Master mode; it is ignored otherwise. It is only possible to set the HIDLE bit during writes to the HCSR. HIDLE is cleared by writing to HTX. To ensure correct transmission of the slave device address byte, HIDLE should be set only when HTX is empty (HTDE = 1). After HIDLE is set, a write to HTX will clear HIDLE and cause the generation of a stop event, a start event, and then the transmission of the eight MSBs of the data as the slave device address byte. While HIDLE is cleared, data written to HTX will be transmitted 'as is.' If the SHI completes transmitting a word and there is no new data in HTX, the clock will be suspended after sampling ACK. If the SHI completes transmitting a word and there is no new data in HTX when HIDLE is set, a stop event will be generated.

HIDLE determines the acknowledge that the receiver sends after correct reception of a byte. If HIDLE is cleared, the reception will be acknowledged by sending a '0' bit on the SDA line at the ACK clock tick. If HIDLE is set, the reception will not be acknowledged (a '1' bit is sent). It is used to signal an end-of-data to a slave transmitter by not generating an ACK on the last byte. As
a result, the slave transmitter must release the SDA line to allow the master to generate the stop event. If the SHI completes receiving a word and the HRX FIFO is full, the clock will be suspended before transmitting an ACK. While HIDLE is cleared the bus is busy, that is, the start event was sent but no Stop event was generated. Setting HIDLE will cause a stop event after receiving the current word.
Note: HIDLE is set while the SHI is not in the I2C Master mode. Care should be taken to ensure that HIDLE be set by the programmer only after disabling any DMA channel service to HTX.
HIDLE is set during hardware reset, software reset, individual reset, and while
the chip is in the Stop state.


HCSR register bit 10

HCSR Bus-Error Interrupt Enable (HBIE)
The read/write HCSR Bus-error Interrupt Enable (HBIE) control bit is used to enable the SHI bus-error interrupt. If HBIE is cleared, bus-error interrupts are disabled, and the HBER status bit must be polled to determine if an SHI bus error occurred. If both HBIE and HBER are set, the SHI will request SHI bus-error interrupt service from the interrupt controller. HBIE is cleared by hardware reset and software reset.
Note: Clearing HBIE will mask a pending bus-error interrupt only after a one-instruction-cycle delay. If HBIE is cleared in a long interrupt service routine, it is recommended that at least one other instruction separate the instruction that clears HBIE and the RTI instruction at the end of the interrupt service routine.


HCSR register bit 11

HCSR Transmit-Interrupt Enable (HTIE)
The read/write HCSR Transmit-Interrupt Enable (HTIE) control bit is used to enable the SHI transmit data interrupts. If HTIE is cleared, transmit interrupts are disabled, and the HTDE status bit must be polled to determine if the SHI transmit-data register is empty. If both HTIE and HTDE are set and HTUE is cleared, the SHI will request SHI transmit-data interrupt service from the interrupt controller. If both HTIE and HTUE are set, the SHI will request SHI transmit-underrun-error interrupt service from the interrupt controller. HTIE is cleared by hardware reset and software reset.
Note: Clearing HTIE will mask a pending transmit interrupt only after a one-instruction cycle-delay. If HTIE is cleared in a long interrupt service routine, it is recommended that at least one other instruction separate the instruction that
clears HTIE and the RTI instruction at the end of the interrupt service routine.


HCSR register bits 12 and 13

HCSR Receive Interrupt Enable (HRIE[1:0])
The read/write HCSR Receive Interrupt Enable (HRIE[1:0]) control bits are used to enable the SHI receive-data interrupts. If HRIE[1:0] are cleared, receive interrupts are disabled, and the HRNE and HRFF (bits 17 and 19, see below) status bits must be polled to determine if there is data in the receive FIFO. If HRIE[1:0] are not cleared, receive interrupts will be generated according to Table
3-6.

HRIE[1:0]    Interrupt                         Condition
00             Disabled                           Not applicable
01             Receive FIFO not empty    HRNE = 1 and HROE = 0
                Receive Overrun Error        HROE = 1
10            Reserved                          Not applicable
11            Receive FIFO full               HRFF = 1 and HROE = 0
               Receive Overrun Error         HROE = 1

Note: HRIE[1:0] are cleared by hardware and software reset.
Note: Clearing HRIE[1:0] will mask a pending receive interrupt only after a one-instruction-cycle delay. If HRIE[1:0] are cleared in a long interrupt service routine, it is recommended that at least one other instruction separate the instruction that clears HRIE[1:0] and the RTI instruction at the end of the interrupt service routine.


HCSR register bit 14

HCSR Host Transmit Underrun Error (HTUE)
The read-only status bit Host Transmit Underrun Error (HTUE) indicates that a transmit-underrun error occurred. Transmit-underrun errors can occur only when operating in the SPI Slave mode or the I2C Slave mode when HCKFR is cleared (in a Master mode, transmission takes place on demand and no underrun can occur). It is set when both the shift register and the HTX register are empty and the external master begins reading the next word:
 When operating in the I2C mode, HTUE is set in the falling edge of the ACK bit. In this case, the SHI will retransmit the previously transmitted word.
 When operating in the SPI mode, HTUE is set at the first clock edge if CPHA = 1;
it is set at the assertion of SS if CPHA = 0.
If a transmit interrupt occurs with HTUE set, the transmit-underrun interrupt vector will be generated. If a transmit interrupt occurs with HTUE cleared, the regular transmit-data interrupt vector will be generated. HTUE is cleared by reading the HCSR and then writing to the HTX register. HTUE is cleared by hardware reset, software reset, SHI individual reset, and during the Stop state.


HCSR register bit 15

HCSR Host Transmit Data Empty (HTDE)
The read-only status bit Host Transmit Data Empty (HTDE) indicates that the HTX register is empty and can be written by the DSP. HTDE is set when the data word is transferred from HTX to the shift register, except for a special case in SPI Master mode when CPHA = 0 (see HCKR). When operating in the SPI Master mode with CPHA = 0, HTDE is set after the end of the data word transmission. HTDE is cleared when HTX is written by the DSP either with write instructions or DMA transfers. HTDE is set by hardware reset, software reset, SHI individual reset, and during the Stop state.


HCSR register bit 17

Host Receive FIFO Not Empty (HRNE)
The read-only status bit Host Receive FIFO Not Empty (HRNE) indicates that the Host Receive FIFO (HRX) contains at least one data word. HRNE is set when the FIFO is not empty. HRNE is cleared when HRX is read by the DSP (read instructions or DMA transfers), reducing the number of words in the FIFO to 0. HRNE is cleared during hardware reset, software reset, SHI individual reset, and during the Stop state.


HCSR register bit 19

Host Receive FIFO Full (HRFF)
The read-only status bit Host Receive FIFO Full (HRFF) indicates that the Host Receive FIFO (HRX) is full. HRFF is set when the HRX FIFO is full. HRFF is cleared when HRX is read by the DSP (read instructions or DMA transfers) and at least one place is available in the FIFO. HRFF is cleared by hardware reset, software reset, SHI individual reset, and during the Stop state.


HCSR register bit 20

Host Receive Overrun Error (HROE)
The read-only status bit Host Receive Overrun Error (HROE) indicates that a data-receive overrun error occurred. Receive-overrun errors can not occur when operating in the I2C Master mode, since the clock is suspended if the receive FIFO is full; it also cannot occur when operating in the I2C Slave mode when HCKFR is set. HROE is set when the shift register (IOSR) is filled and ready to transfer the data word to the HRX FIFO and the FIFO is already full (HRFF is set). When a receive-overrun error occurs, the shift register is not transferred to the FIFO. If a receive interrupt occurs with HROE set, the receive-overrun interrupt vector will be generated. If a receive interrupt occurs with HROE cleared, the regular receive-data interrupt vector will be generated. HROE is cleared by reading the HCSR with HROE set, followed by reading HRX. HROE is cleared by hardware reset, software reset, SHI individual reset, and during the Stop state.


HCSR register bit 21

Host Bus Error (HBER)
The read-only status bit Host Bus Error (HBER) indicates that an SHI bus error occurred when operating as a master (HMST set). In I2C mode, HBER is set if the transmitter does not receive an acknowledge after a byte is transferred; in this case, a stop event will be generated and then transmission will be suspended. In SPI mode, the bit is set if !SS is asserted; in this case, transmission is suspended at the end of transmission of the current word. HBER is cleared only by hardware reset, software reset, SHI individual reset, and during the Stop state.


HCSR register bit 22

HCSR Host Busy (HBUSY)
The read-only status bit Host Busy (HBUSY) indicates that the I 2 C bus is busy (when in the I2C mode) or that the SHI itself is busy (when in the SPI mode). When operating in the I2C mode, HBUSY is set after the SHI detects a Start event and remains set until a Stop event is detected.


SHI  SPI BUS

The SPI bus consists of two serial data lines (MISO and MOSI), a clock line (SCK), and a Slave Select line (SS).During an SPI transfer, a byte is shifted out one data pin while a different byte is simultaneously shifted in through a second data pin. It can be viewed as two 8-bit shift registers connected together in a circular manner, where one shift register is located on the master side and the other on the slave side. Thus the data bytes in the master device and slave device are effectively exchanged. The MISO and MOSI data pins are used for transmitting and receiving serial data.
When the SPI is configured as a master, MISO is the master data input line, and MOSI is the master data output line. When the SPI is configured as a slave device, these pins reverse roles. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices.
When the SPI is configured as a master, the control bits in the HCKR select the appropriate clock rate, as well as the desired clock polarity and phase format (see SPI Data-To-Clock Timing Diagram). The SS line allows individual selection of a slave SPI device; slave devices that are not selected do not interfere with SPI bus activity (i.e., they keep their MISO output pin in the high-impedance state). When the SHI is configured as an SPI master device, the SS line should be held high. If the SS line is driven low when the SHI is in SPI Master mode, a bus error will be generated (the HCSR HBER bit will be set).


SHI I2C BUS

The I2C serial bus consists of two bi-directional lines, one for data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor.
Note: Within the I 2 C bus specifications, the standard mode (100 kHz clock rate) and a fast mode (400 kHz clock rate) are defined. The SHI may operate in both modes.


SHI Receive Interrupt Enable Bits Table

HRIE[1:0]    Interrupt                        Condition
       00          Disabled                       Not applicable

       01          ReceiveFIFO not empty HRNE = 1 and HROE = 0
                    Receive Overrun Error    HROE = 1

       10         Reserved                      Not applicable

       11        Receive FIFO full           HRFF = 1 and HROE = 0
                  Receive Overrun Error     HROE = 1


SHI register IOSR
IOSR I/O Shift Register

SHI   Host Side

The variable length Input/Output Shift Register (IOSR) can be viewed as a serial-to-parallel and parallel-to-serial buffer in the SHI. The IOSR is involved with every data transfer in both directions (read and write). In compliance with the I 2 C and SPI bus protocols, data is shifted in and out MSB first. In single-byte data transfer modes, the most significant byte of the IOSR is used as the shift register. In 16-bit data transfer modes, the two most significant bytes become the shift register. In 24-bit transfer modes, the shift register uses all three bytes of the IOSR (seediagram below):
Note: The IOSR cannot be accessed directly either by the host processor or by the DSP. It is fully controlled by the SHI controller logic.


ESAI
ESAI Enhanced Serial Audio Interface

INTRODUCTION

ESAI Control and Data Pins

ESAI Registers

ESAI Operating Modes

ESAI Interrupt Requests

GPIO Port C


ESAI Introduction

The Enhanced Synchronous Serial Interface (ESAI) provides a full-duplex serial port for serial communication with a variety of serial devices including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals which implement the Motorola SPI serial protocol.
The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator. It is a superset of the 56300 Family ESSI peripheral and of the 56000 Family SAI peripheral.

The ESAI is named synchronous because all serial transfers are synchronized to a clock. Additional synchronization signals are used to delineate the word frames. The normal mode of operation is used to transfer data at a periodic rate, one word per period. The network mode is similar in that it is also intended for periodic transfers; however, it will support up to 32 words (time slots) per period. This mode can be used to build time division multiplexed (TDM) networks. In contrast, the on-demand mode is intended for non-periodic transfers of data, to transfer data serially at high speed when the data becomes available. This mode offers a subset of the SPI protocol.

See also:

ESAI Block Diagram.


ESAI Block Diagram


ESAI Control and Data Pins

Three to twelve pins are required for operation, depending on the operating mode selected and the number of transmitters and receivers enabled. The SDO0 and SDO1 pins are used by transmitters 0 and 1 only. The SDO2/SDI3, SDO3/SDI2, SDO4/SDI1 and SDO5/SDI0 pins are shared by transmitters 2 to 5 with receivers 0 to 3. The actual mode of operation is selected under software control. All transmitters operate fully synchronized under control of the same transmitter clock signals. All receivers operate fully synchronized under control of the same receiver clock signals.

ESAI Serial Transmit Data Pin (SDO0)
ESAI Serial Transmit Data Pin (SDO1)
ESAI Serial Transmit/Receive Data Pin (SDO2/SDI3)
ESAI Serial Transmit/Receive Data Pin (SDO3/SDI2)
ESAI Serial Transmit/Receive Data Pin (SDO4/SDI1)
ESAI Serial Transmit/Receive Data Pin (SDO5/SDI0)
ESAI Receiver Serial Clock (SCKR)
ESAI Transmitter Serial Clock (SCKT)
ESAI Frame Sync for Receiver (FSR)
ESAI Frame Sync for Transmitter (FST)
ESAI High Frequency Clock for Transmitter (HCKT)
ESAI High Frequency Clock for Receiver (HCKR)


ESAI Registers

ESAI Transmit Clock Control Register (TCCR)

ESAI Transmit Control Register (TCR)

ESAI Receive Clock Control Register (RCCR)

ESAI Receive Control Register (RCR)

ESAI Common Control Register (SAICR)

ESAI Status Register (SAISR)

ESAI Transmit Slot Mask Register A (TSMA)

ESAI Transmit Slot Mask Register B (TSMB)

ESAI Receive Slot Mask Register A (RSMA)

ESAI Receive Slot Mask Register B (RSMB)


ESAI register TCCR
Transmit Clock Control Register TCCR

ESAI

The read/write Transmitter Clock Control Register  TCCR controls the ESAI transmitter clock generator bit and frame sync rates, the bit rate and high frequency clock sources and the directions of the HCKT, FST and SCKT signals. In synchronous mode, the bit clock defined for the transmitter determines the receiver bit clock as well. TCCR also controls the number of words per frame for the serial data.
Hardware and software reset clear all the bits of the TCCR register.

Bits 7-0:    PM7-TPM0     TCCR Prescale Modulus Select

Bit 8:        TPSR             TCCR Prescaler Range

Bits 13-9:  TDC4-TDC0   TCCR Frame Rate Divider Control

Bits 17-14: TFP3-TFP0   TCCR Transmitter High Frequency Clock Divider

Bit 18:       TCKP            TCCR Transmitter Clock Polarity

Bit 19:       TFSP            TCCR Transmitter Frame Sync Polarity

Bit 20:      THCKP          TCCR Transmitter High Frequency Clock Polarity

Bit21:       TCKD            TCCR Transmitter Clock Source Direction

Bit 22:      TFSD            TCCR Frame Sync Signal Direction

Bit 23:      THCKD         TCCR High Frequency Clock Direction

See also:

ESAI Clock Generator Functional Block Diagram

ESAI Frame Sync Generator Functional Block Diagram


TCCR register bit  7 to 0
TCCR Prescale Modulus Select Bits

The TPM7-TPM0 bits specify the divide ratio of the prescale divider in the ESAI transmitter clock generator. A divide ratio from 1 to 256 (TPM[7:0]=$00 to $FF) may be selected. The bit clock output is available at the transmit clock (SCKT) pin of the DSP. The bit clock output is also available internally for use as the bit clock to shift the transmit and receive shift registers.
Careful choice of the crystal oscillator frequency and the prescaler modulus will allow the industry-standard codec master clock frequencies of 2.048 MHz, 1.544 MHz, and 1.536 MHz to be generated.


TCCR register bit  8
TCCR Bit 8

The TPSR controls a fixed divide-by-eight prescaler in series with the variable prescaler. This bit is used to extend the range of the prescaler for those cases where a slower bit clock is desired. When TPSR is set, the fixed prescaler is bypassed. When TPSR is cleared, the fixed divide-by-eight prescaler is operational. The maximum internally generated bit clock frequency is Fosc/4, the minimum internally generated bit clock frequency is:
Fosc/(2 x 8 x 256)=Fosc/4096.
NOTE The combination TPSR = 1 and TPM7-TPM0 = $00 is forbidden and may cause synchronization problems if used.


TCCR register bit 13 to 9
TCCR bits 13 to 9

ESAI register TCCR Frame Rate Divider Control (TDC4–TDC0) - Bits 9–13
The TDC4–TDC0 bits control the divide ratio for the programmable frame rate dividers used to generate the transmitter frame clocks. In network mode, this ratio may be interpreted as the number of words per frame minus one. The
divide ratio may range from 2 to 32 (TDC[4:0]=00001 to 11111) for network mode. A divide ratio of one (TDC[4:0]=00000) in network mode is a special case (on-demand mode). In normal mode, this ratio determines the word transfer rate. The divide ratio may range from 1 to 32 (TDC[4:0]=00000 to 11111) for normal mode. In normal mode, a divide ratio of one (TDC[4:0]=00000) provides continuous periodic data word transfers. A bit-length sync (TFSL=1)
must be used in this case.


TCCR register bit 17 to 14
TCCR Bits 17 to 14

TCCR Transmitter High Frequency Clock Divider (TFP3–TFP0) - Bits 14–17
The TFP3–TFP0 bits control the divide ratio of the transmitter high frequency clock to the transmitter serial bit clock when the source of the high frequency clock and the bit clock is the internal DSP clock. When the HCKT input is being driven from an external high frequency clock, the TFP3-TFP0 bits specify an additional division ration in the clock divider chain.

Transmitter High Frequency Clock Divider
TFP3-TFP0 Divide Ratio
$0               1
$1               2
$2               3
... ...
$F             16


TCCR register bit 18
TCCR Bit 18

TCCR Transmitter Clock Polarity (TCKP) - Bit 18
The Transmitter Clock Polarity (TCKP) bit controls on which bit clock edge data and frame sync are clocked out and latched in. If TCKP is cleared the data and the frame sync are clocked out on the rising edge of the transmit bit clock and latched in on the falling edge of the receive bit clock. If TCKP is set the falling edge of the transmit clock is used to clock the data out and frame sync
and the rising edge of the receive clock is used to latch the data and frame sync in.


TCCR register bit 19
TCCR bit 19

The Transmitter Frame Sync Polarity (TFSP) bit determines the polarity of the transmit frame sync signal. When TFSP is cleared, the frame sync signal polarity is positive (i.e the frame start is indicated by a high level on the frame sync pin). When TFSP is set, the frame sync signal polarity is negative (i.e the frame start is indicated by a low level on the frame sync pin).


TCCR register bit 20
TCCR bit 20

TCCR Transmitter High Frequency Clock Polarity (THCKP) - Bit 20
The Transmitter High Frequency Clock Polarity (THCKP) bit controls on which bit clock edge data and frame sync are clocked out and latched in. If THCKP is cleared the data and the frame sync are clocked out on the rising edge of the transmit bit clock and latched in on the falling edge of the receive bit clock. If THCKP is set the falling edge of the transmit clock is used to clock the data out and frame sync and the rising edge of the receive clock is used to latch the data and frame sync in.


TCCR register bit 21
TCCR bit 21

TCCR Transmitter Clock Source Direction (TCKD) - Bit 21
The Transmitter Clock Source Direction (TCKD) bit selects the source of the clock signal used to clock the transmit shift register in the asynchronous mode and all the transmit shift register(s) and the receive shift register in the synchronous mode. In asynchronous mode when TCKD is set, the internal clock source becomes the bit clock for the transmit shift register and word length divider and is the output on the SCKT pin. When TCKD is cleared, the clock source is external; the internal clock generator is disconnected from the SCKT pin, and an external clock source may drive this pin.


TCCR register bit 22
TCCR bit 22

TFSD controls the direction of the FST I/O pin. When TFSD is cleared, FST is an input; when TFSD is set, FST is an output.


TCCR register bit 23
TCCR bit 23

THCKD controls the direction of the HCKT I/O pin. When THCKD is cleared, HCKT is an input; when THCKD is set, HCKT is an output.


ESAI Clock Generator Functional Block Diagram


ESAI Generator Block Diagram
ESAI Frame Sync Generator Functional Block Diagram


ESAI register TCR

The read/write Transmit Control Register (TCR) ) controls the ESAI transmitter
section. Interrupt enable bits for the transmitter section are provided in this control register. Operating modes are also selected in this register.
Hardware and software reset clear all the bits in the TCR register.

Bit 5-0     TE5-TE0                 ESAI Transmit # 5-#0 Enable

Bit 6        TSHFD                   Transmitter Shift Direction

Bit 7        TWA                       Transmitter Word Alignment Control

Bits 9-8    TMOD1-TMOD0  Transmitter Network Mode Control

Bits 14-10 TSWS4-TSWS0 Transmitter Slot and Word Length Select

Bit 15       TFSL                      Transmitter Frame Sync Length

Bit 16       TFSR                     Transmitter Frame Sync Relative Timing

TCR Reserved Bits - Bits 17-19

Bit 20       TEIE                     ESAI Transmit Exception Interrupt Enable

Bit 21       TEDIE                 ESAI Transmit Even Slot Data Interrupt Enable

Bit 22       TIE                       ESAI Transmit Interrupt Enable

Bit 23       TLIE                     ESAI Transmit Last Slot Interrupt Enable


ESAI register TCR bit 0 to 5
TCR register bits 0 - 5

TCR  ESAI Transmit # 5-#0 Enable bits (TE5-TE0)   x=0,...,5
TEx enables the transfer of data from TXx to the transmit shift register #x. When TEx is set and a frame sync is detected, the transmit #1 portion of the ESAI is enabled for that frame. When TEx is cleared, the transmitter #1 will be disabled after completing transmission of data currently in the ESAI transmit shift register. The SDO1 output is three-stated, and any data present in TXx  will not be transmitted (i.e., data can be written to TXx with TEx cleared; but data will not be transferred to the transmit shift register #x). The normal mode transmit enable sequence is to write data to one or more transmit data registers before setting TEx. The normal transmit disable sequence is to clear TEx, TIE and TEIE after TDE equals one. In the network mode, the operation of clearing TEx and setting it again will disable the transmitter #x after completing transmission of the current data word until the beginning of the next frame. During that time period, the SDO1 pin will remain in the high-impedance state. The on-demand mode transmit enable sequence can be the same as the normal mode, or TEx can be left enabled.


ESAI register TCR bit 6
TCR bit 6

 Transmitter Shift Direction (TSHFD) bit 6 causes the transmit shift register(s) to shift data out MSB first when TSHFD equals zero or LSB first when TSHFD equals one.


ESAI register TCR bit 7
TCR bit 7

The Transmitter Word Alignment Control (TWA) bit 7 defines the alignment of the data word in relation to the slot. This is relevant for the cases where the word length is shorter than the slot length. If TWA is cleared, the data word is left-aligned in the slot frame during transmission. If TWA is set, the data word is right-aligned in the slot frame during transmission.
Since the data word is shorter than the slot length, the data word will be extended until achieving the slot length, according to the following rule:

1. If the data word is left-aligned (TWA=0), then the last data bit will be repeated after the data word has been transmitted.
2. If the data word is right-aligned (TWA=1), then the first data bit will be repeated before the trans-mission of the data word.


ESAI register TCR bits 8 to 9
TCR bits 8 to 9

Transmitter Network Mode Control
The TMOD1 and TMOD0 bits are used to define the network mode of ESAI transmitters. In the normal mode, the frame rate divider determines the word transfer rate – one word is transferred per frame sync during the frame sync time slot. In network mode, a word is (possibly) transferred every time slot.

In order to comply with AC-97 specifications TSWS4-TSWS0 should be set to 00011 (20-bit slot, 20-bit word), TFSL and TFSR should be cleared, and TDC4-TDC0 should be set to $0C (13 words in frame).


ESAI register TCR bits 10 to 14
TCR bits 10 -14

The RSWS4-RSWS0 bits are used to select the length of the slot and the length of the data words being received via the ESAI. The word length must be equal to or shorter than the slot length. The possible combinations are shown in Table below.


ESAI register TCR bit 15
TCR bit 15

Transmitter Frame Sync Length (TFSL)
The TFSL bit selects the length of frame sync to be generated or recognized. If TFSL is cleared, a word-length frame sync is selected. If TFSL is set, a 1-bit clock period frame sync is selected.


ESAI register TCR bit 16
TCR bit 16

Transmitter Frame Sync Relative Timing (TFSR)
TFSR determines the relative timing of the receive and transmit frame sync signal as referred to the serial data lines, for a word length frame sync only. When TFSR is cleared the word length frame sync occurs together with the first bit of the data word of the first slot. When TFSR is set the word length frame sync occurs one serial clock cycle earlier (i.e together with the last bit of the previous data word).


ESAI register TCR bit 20
TCR bit 20

ESAI Transmit Exception Interrupt Enable (TEIE)
When TEIE is set, the DSP will be interrupted when both TDE and TUE in the ESAI status register are set. When TEIE is cleared, this interrupt is disabled. Reading the status register followed by writing to all the data registers of the enabled transmitters will clear TUE, thus clearing the pending interrupt.

ESAI Transmit Data with Exception Status
Occurs when the transmit exception interrupt is enabled (TEIE=1), at least one transmit data register of the enabled transmitters is empty, and a transmitter underrun error has occurred (TUE=1). TUE is cleared by first reading the SAISR and then writing to all the transmit data registers of the enabled transmitters, or to the TSR to clear the pending interrupt.


ESAI register TCR bit 21
TCR bit 21

ESAI Transmit Even Slot Data Interrupt Enable (TEDIE)
The DSP will be interrupted when TEDIE bit and the TEDE flag in the ESAI status register are set. When TEDIE is cleared, this interrupt is disabled. Writing data to all the data registers of the enabled transmitters or to TSR will clear TDE, thus clearing the interrupt. Transmit interrupts with exception have higher priority than normal transmit data interrupts, therefore if exception occurs (TUE is set) and TEIE is set the ESAI will request an ESAI transmit data with exception interrupt from the interrupt controller.

ESAI Transmit Even-Data
Occurs when the transmit even slot data interrupt is enabled (TEDIE=1), at least one of the enabled transmit data registers is empty (TDE=1), the slot is an even slot (TEDE=1), and no exception occurred (TUE=0 or TEIE=0). Writing to all the TX registers of the enabled transmitters, or to the TSR will clear this interrupt request.


ESAI register TCR bit 22
TCR bit 22

ESAI Transmit Interrupt Enable (TIE)
The DSP will be interrupted when TIE and the TDE flag in the ESAI status register are set. When TIE is cleared, this interrupt is disabled. Writing data to all the data registers of the enabled transmitters or to TSR will clear TDE, thus clearing the interrupt. Transmit interrupts with exception have higher priority than normal transmit data interrupts, therefore if exception occurs (TUE is set) and TEIE is set the ESAI will request an ESAI transmit data with exception interrupt from the interrupt controller.


ESAI register TCR bit 23
TCR bit 23

ESAI Transmit Last Slot Interrupt Enable (TLIE)
TLIE enables an interrupt at the beginning of last slot of a frame in network mode. When TLIE is set the DSP will be interrupted at the start of the last slot in a frame in network mode regardless of the transmit mask register setting. When TLIE is cleared the transmit last slot interrupt is disabled. TLIE is disabled when DC= $0 (on-demand mode).

ESAI Transmit Last slot interrupt
Occurs, if enabled (TLIE=1), at the start of the last slot of the frame in network mode regardless of the transmit mask register setting. The Transmit Last slot interrupt may be used for resetting the transmit mask slot register, reconfigure the DMA channels and reassignment of data memory pointers. Using the Transmit last slot interrupt guarantees that the previous frame was serviced with the previous setting and the new frame will be serviced with the new setting without synchronization problems. Note that the maximum Transmit last slot interrupt service time should not exceed N-1 ESAI bits service time (Where N is the number of bits in a slot).


ESAI register RCCR

The read/write Receive Clock Control Register (RCCR) controls the ESAI receiver clock generator bit and frame sync rates, word length, and number of words per frame for the serial data.
Hardware and software reset clear all the bits of the RCCR register.

Bits 7–0      RPM7–RPM0   Prescale Modulus Select

Bit 8           RPSR              Prescaler Range

Bits 9–13   RDC4–RDC0     Frame Rate Divider Control

Bits 14-17  RFP3-RFP0      Receiver High Frequency Clock Divider

Bit 18        RCKP               Receiver Clock Polarity

Bit 19        RFSP               Receiver Frame Sync Polarity

Bit 20       RHCKP             Receiver High Frequency Clock Polarity

Bit 21       RCKD               Receiver Clock Source Direction

Bit 22       RFSD               Frame Sync Signal Direction

Bit 23       RHCKD             High Frequency Clock Direction

ESAI receive clock generator functional diagram

ESAI frame sync generator functional diagram


RCCR register bits 7 to 0

RCCR Prescale Modulus Select (RPM7–RPM0)
The RPM7–RPM0 bits specify the divide ratio of the prescale divider in the ESAI receiver clock generator. A divide ratio from 1 to 256 (RPM[7:0]=0 to $FF) may be selected. The bit clock output is available at the receive clock (SCKR) pin of the DSP. The bit clock output is also available internally for use as the bit clock to shift the receive shift registers. Careful choice of the crystal oscillator frequency and the prescaler modulus will allow the industry-standard codec master clock frequencies of 2.048 MHz, 1.544 MHz, and 1.536 MHz to be generated.


RCCR register bit 8

RCCR Prescaler Range (RPSR)
The RPSR controls a fixed divide-by-eight prescaler in series with the variable prescaler. This bit is used to extend the range of the prescaler for those cases where a slower bit clock is desired. When RPSR is set, the fixed prescaler is bypassed. When RPSR is cleared, the fixed divide-by-eight prescaler is operational. The maximum internally generated bit clock frequency is Fosc/4, the minimum internally generated bit clock frequency is Fosc/(2 x 8 x 256)=Fosc/4096.
NOTE The combination RPSR = 1 and RPM7-RPM0 = $00 is forbidden and may cause synchronization problems if used.


RCCR register bits 9 to 13

RCCR Frame Rate Divider Control (RDC4–RDC0)
The RDC4–RDC0 bits control the divide ratio for the programmable frame rate dividers used to generate the receiver frame clocks.
In network mode, this ratio may be interpreted as the number of words per frame minus one. The divide ratio may range from 2 to 32 (RDC[4:0]=00001 to 11111) for network mode. A divide ratio of one (RDC[4:0]=00000) in network mode is a special case (on-demand mode).
In normal mode, this ratio determines the word transfer rate. The divide ratio may range from 1 to 32 (RDC[4:0]=00000 to 11111) for normal mode. In normal mode, a divide ratio of one (RDC[4:0]=00000) provides continuous periodic data word transfers. A bit-length sync (RFSL=1) must be used in this case.


RCCR register bits 14 to 17

RCCR Receiver High Frequency Clock Divider (RFP3-RFP0)
The RFP3–RFP0 bits control the divide ratio of the receiver high frequency clock to the receiver serial bit clock when the source of the receiver high frequency clock and the bit clock is the internal DSP clock. When the HCKR input is being driven from an external high frequency clock, the RFP3-RFP0 bits specify an additional division ration in the clock divider chain.
See also ESAI receive clock generation functional diagram.

Receiver High Frequency Clock Divider
RFP3-RFP0   Divide Ratio
$0                 1
$1                 2
$2                 3
... ...
$F              16


RCCR register bit 18

RCCR Receiver Clock Polarity (RCKP)
The Receiver Clock Polarity (RCKP) bit controls on which bit clock edge data and frame sync are clocked out and latched in. If RCKP is cleared the data and the frame sync are clocked out on the rising edge of the receive bit clock and latched in on the falling edge of the receive bit clock. If RCKP is set the falling edge of the receive clock is used to clock the data out and frame sync and the rising edge of the receive clock is used to latch the data and frame sync in.


RCCR register bit 19

RCCR Receiver Frame Sync Polarity (RFSP)
The Receiver Frame Sync Polarity (RFSP) determines the polarity of the receive frame sync signal. When RFSP is cleared the frame sync signal polarity is positive (i.e the frame start is indicated by a high level on the frame sync pin). When RFSP is set the frame sync signal polarity is negative (i.e the frame start is indicated by a low level on the frame sync pin).


RCCR register bit 20

RCCR Receiver High Frequency Clock Polarity (RHCKP)
The High Frequency Clock Polarity (RHCKP) bit controls on which bit clock edge data and frame sync are clocked out and latched in. If RHCKP is cleared the data and the frame sync are clocked out on the rising edge of the receive bit clock and latched in on the falling edge of the receive bit clock. If RHCKP is set the falling edge of the receive clock is used to clock the data out and frame sync and the rising edge of the receive clock is used to latch the data and frame sync in.


RCCR register bit 21

RCCR Receiver Clock Source Direction (RCKD)
The Receiver Clock Source Direction (RCKD) bit selects the source of the clock signal used to clock the receive shift register in the asynchronous mode and the IF0/OF0 direction at the synchronous mode. In asynchronous mode when RCKD is set, the internal clock source becomes the bit clock for the transmit shift register and word length divider and is the output on the SCKR pin. When RCKD is cleared, the clock source is external; the internal clock generator is  disconnected from the SCKR pin, and an external clock source may drive this pin.


RCCR register bit 22

RCCR Frame Sync Signal Direction (RFSD)
RFSD controls the direction of the FSR I/O pin. When RFSD is cleared, FSR is an input; when RFSD is set, FSR is an output.


RCCR register bit 23

RCCR High Frequency Clock Direction (RHCKD)
RHCKD controls the direction of the HCKR I/O pin. When RHCKD is cleared, HCKR is an input; when RHCKD is set, HCKR is an output.


ESAI register RCR

The read/write Receive Control Register (RCR) (see Figure 4-5) controls the ESAI receiver section. Interrupt enable bits for the receivers are provided in this control register. The number of receiver are enabled in this register (0,1,2 or 3 receivers can be enabled) if the input data pin is not used by a transmitter. Operating modes are also selected in this register. Hardware and software reset clear all the bits in the RCR register.

Bit 3-0      RE3- RE0     ESAI Receive Enable

RCR Reserved Bits - Bits 4-5, 17-19

Bit 6         RSHF           Receiver Shift Direction

Bit 7         RWA            Receiver Word Alignment Control

Bits 8-9     RMOD1-0     Receiver Network Mode Control

Bits 10-14 RSWS4-0     Receiver Slot and Word Select

Bit 15       RFSL           Receiver Frame Sync Length

Bit 16       RFSR          Receiver Frame Sync Relative Timing

Bit 20       REIE           ESAI Receive Exception Interrupt Enable

Bit 21       REDIE         ESAI Receive Even Slot Data Interrupt Enable

Bit 22       RIE             ESAI Receive Interrupt Enable

Bit 23       RLIE           ESAI Receive Last Slot Interrupt Enable


RCR register bits 3 to 0

RCR ESAI Receive Enable (REx)
When REx is set and TEy is cleared, the receive x of the ESAI is enabled and sample data at SDO4/SDI1. When RE1 bit is cleared, the receiver will be disabled by inhibiting data transfer into RXx. If data is being received while this bit is cleared, the remainder of the word will be shifted in and transferred to the ESAI receive data registers.
REx must be set in the normal mode and on-demand mode to receive data. In network mode, the operation of clearing REx and setting it again will disable the receiver after reception of the current data word until the beginning of the next data frame.

x=0,...,3  y=5-x


RCR register bit 6

RCR Receiver Shift Direction (RSHFD)
This bit causes the receiver shift register(s) to shift data in MSB first when RSHFD equals zero or LSB first when RSHFD equals one.


RCR register bit 7

RCR Receiver Word Alignment Control (RWA)
The Receiver Word Alignment Control (RWA) defines the alignment of the data word in relation to the slot. This is relevant for the cases where the word length is shorter than the slot length. If RWA is cleared, the data word is assumed to be left-aligned in the slot frame. If RWA is set, the data word is assumed to be right-aligned in the slot frame. Since the data word is shorter than the slot length, the data bits which are not in the data word field will be ignored. For data word lengths of less than 24 bits, the data word will be right-extended with zeroes before being stored in the receive data registers.


RCR register bits 8 to 9

RCR Receiver Network Mode Control (RMOD1-RMOD0)
The RMOD1 and RMOD0 bits are used to define the network mode of ESAI transmitters according to Table below. In the normal mode, the frame rate divider determines the word transfer rate – one word is transferred per frame sync during the frame sync time slot. In network mode, a word is (possibly) transferred every time slot. For more details, see Section 4.4.
In order to comply with AC-97 specifications RSWS4-RSWS0 should be set to 00011 (20-bit slot, 20-bit word), RFSL and RFSR should be cleared, and RDC4-RDC0 should be set to $0C (13 words in frame).

ESAI Receive Network Mode Selection Table

RMOD1 RMOD0            Network Mode
     0           0                   Normal Mode
     0           1                   Network Mode
     1           0                   Reserved
     1           1                   AC97


RCR register bits 10 to 14

RCR Receiver Slot and Word Select (RSWS4-RSWS0)
The RSWS4-RSWS0 bits are used to select the length of the slot and the length of the data words being received via the ESAI. The word length must be equal to or shorter than the slot length. The possible combinations are shown in table below.

RSWS4-0      SLOT LENGTH     WORD LENGTH
0 0 0 0 0            8                          8
0 0 1 0 0          12                          8
0 0 0 0 1                                      12
0 1 0 0 0          16                          8
0 0 1 0 1                                      12
0 0 0 1 0                                      16
0 1 1 0 0          20                          8
0 1 0 0 1                                      12
0 0 1 1 0                                      16
0 0 0 1 1                                      20
1 0 0 0 0          24                          8
0 1 1 0 1                                      12
0 1 0 1 0                                      16
0 0 1 1 1                                      20
1 1 1 1 0                                      24
1 1 0 0 0          32                          8
1 0 1 0 1                                      12
1 0 0 1 0                                      16
0 1 1 1 1                                      20
1 1 1 1 1                                      24


RCR register bit 15

RCR Receiver Frame Sync Length (RFSL)
The RFSL bit selects the length of frame sync to be generated or recognized. If RFSL is cleared, a word-length frame sync is selected. If RFSL is set, a 1-bit clock period frame sync is selected.


RCR register bit 16

RCR Receiver Frame Sync Relative Timing (RFSR)
RFSR determines the relative timing of the receive and receive frame sync signal as referred to the serial data lines, for a word length frame sync only. When RFSR is cleared the word length frame sync occurs together with the first bit of the data word of the first slot. When RFSR is set the wordlength frame sync occurs one one serial clock cycle earlier (i.e together with the last bit of the previous data word).


RCR register bit 20

RCR ESAI Receive Exception Interrupt Enable (REIE)
When REIE is set, the DSP will be interrupted when both RDF and ROE in the ESAI status register are set. When REIE is cleared, this interrupt is disabled. Reading the status register followed by reading the receive data register will clear ROE, thus clearing the pending interrupt.

ESAI Receive Data with Exception Status.
Occurs when the receive exception interrupt is enabled (REIE=1 in the RCR register), at least one of the enabled receive data registers is full, and a receiver overrun error has occurred (ROE=1 in the SAISR register). ROE is cleared by first reading the SAISR and then reading one of RX3,
RX2, RX1, RX0.


RCR register bit 21

RCR ESAI Receive Even Slot Data Interrupt Enable (REDIE)
When REDIE is set, the DSP will be interrupted when REDF in the ESAI status register is set.
When REDIE is cleared, this interrupt is disabled. Reading the receive data register will clear REDF, thus clearing the pending interrupt.
Receive interrupts with exception have higher priority than normal receive data interrupts, therefore if exception occurs (ROE is set) and REIE is set the ESAI will request an ESAI receive data with exception interrupt from the interrupt controller.

ESAI Receive Even-Data
Occurs when the receive even slot data interrupt is enabled (REDIE=1), at least one of the enabled receive data registers is full (RDF=1), the data is from an even slot (REDF=1), and no exception occurred (ROE=0 or REIE=0). Reading all enabled receiver data registers clears RDF and REDF.


RCR register bit 22

RCR ESAI Receive Interrupt Enable (RIE)
When RIE is set, the DSP will be interrupted when RDF in the ESAI status register is set.
When RIE is cleared, this interrupt is disabled. Reading the receive data register will clear RDF, thus clearing the pending interrupt.
Receive interrupts with exception have higher priority than normal receive data interrupts, therefore if exception occurs (ROE is set) and REIE is set the ESAI will request an ESAI receive data with exception interrupt from the interrupt controller.

ESAI Receive Data
Occurs when the receive interrupt is enabled (RIE=1), at least one of the enabled receive data registers is full (RDF=1), no exception occurred (ROE=0 or REIE=0), and no even slot interrupt occurred (REDF=0 or REDIE=0).
Reading all enabled receiver data registers clears RDF.


RCR register bit 23

RCR ESAI Receive Last Slot Interrupt Enable (RLIE)
RLIE enables an interrupt after the last slot of a frame ended in network mode only.
When RLIE  is set the DSP will be interrupted after the last slot in a frame ended regardless of the receive mask register setting. When RLIE is cleared the receive last slot interrupt is disabled. Hardware and software reset clear RLIE. RLIE is disabled when DC = $0 (on-demand mode).

ESAI Receive Last Slot Interrupt
Occurs, if enabled (RLIE=1), after the last slot of the frame ended (in network mode only) regardless of the receive mask register setting. The Receive Last slot interrupt may be used for resetting the receive mask slot register, reconfigure the DMA channels and reassignment of data memory pointers. Using the Receive last slot interrupt guarantees that the previous frame was serviced with the previous setting and the new frame will be serviced with the new setting without synchronization problems. Note that the maximum Receive last slot interrupt service time should not exceed N-1 ESAI bits service time (Where N is the number of bits in a slot).


ESAI Register SAICR

The read/write Common Control Register (SAICR) contains control bits for functions that use both
the receive and transmit sections of the ESAI.
Hardware and software reset clear all the bits in the SAICR register.

Bits 0-2         OF0-OF2   SAICR Serial Output Flags 0-2

Bits 3-5, 9-23 RESERVED, read as zero, and they should be written with zero for future compatibility.

Bit 6              SYN           SAICR Synchronous Mode Selection

Bit 7              TEBE          SAICR Transmitter External Buffer Enable

Bit 8              ALC             SAICR Alignment Control


SAICR register bit 0 to 2
SAICR register bit 0 -2

SAICR Serial Output Flag 0-2 (OF0 -OF2)
The Serial Output Flag 0 (OF0) is a data bit used to hold data to be send to the OF0 pin. When the ESAI is in the synchronous clock mode (SYN=1), the SCKR pin is configured as the ESAI flag 0. If the receiver serial clock direction bit (RCKD) is set, the SCKR pin is the output flag OF0, and data present in the OF0 bit will be written to the OF0 pin at the beginning of the frame in normal mode or at the beginning of the next time slot in network mode.

SAICR Serial Output Flag 1 (OF1) - Bit 1
The Serial Output Flag 1 (OF1) is a data bit used to hold data to be send to the OF1 pin. When the ESAI is in the synchronous clock mode (SYN=1), the FSR pin is configured as the ESAI flag 1. If the receiver frame sync direction bit (RFSD) is set and the TEBE bit is cleared, the FSR pin is the output flag OF1, and data present in the OF1 bit will be written to the OF1 pin at the beginning of the frame in normal mode or at the beginning of the next time slot in network mode.

SAICR Serial Output Flag 2(OF2) - Bit 2
The Serial Output Flag 2 (OF2) is a data bit used to hold data to be send to the OF2 pin. When the ESAI is in the synchronous clock mode (SYN=1), the HCKR pin is configured as the ESAI flag 2. If the receiver high frequency clock direction bit (RHCKD) is set, the HCKR pin is the output flag OF2, and data present in the OF2 bit will be written to the OF2 pin at the beginning of the frame in normal mode or at the beginning of the next time slot in network mode.


SAICR register bit 6

Synchronous Mode Selection (SYN)
The Synchronous Mode Selection (SYN) bit controls whether the receiver and transmitter sections of the ESAI operate synchronously or asynchronously with respect to each other. When SYN is cleared, asynchronous mode is chosen and independent clock and frame sync signals are used for the transmit and receive sections. When SYN is set, synchronous mode is chosen and the transmit and receive sections use common clock and frame sync signals.
When in the synchronous mode (SYN=1), the transmit and receive sections use the transmitter section clock generator as the source of the clock and frame sync for both sections. Also, the receiver clock pins SCKR, FSR and HCKR now operate as I/O flags. Seetable below for a summary of the effects of SYN on the receiver clock pins.

Mode and Pin Definition Table
Control Bits                    ESAI PINS
SYN TEBE RFSD           SCKR    FSR    HRCK
   0     X        X                SCKR    FSR    HRCK
   1     0        X                F0          F1      F2
    1    1        1                F0       Trans.    F2
                                                Buffer
                                                Enable


SAICR register bit 7

SAICR Transmitter External Buffer Enable (TEBE)
The Transmitter External Buffer Enable (TEBE) bit controls the function of the FSR pin when in the synchronous mode. If the ESAI is configured for operation in the  synchronous mode (SYN=1), and TEBE is set while FSR pin is configured as an output (RFSD=1), the FSR pin will function as the transmitter external buffer enable control, to enable the use of an external buffers on the transmitter outputs. If TEBE is cleared then the FSR pin will function as the serial I/O flag 1. See table below for a summary of the effects of TEBE on the FSR pin.

Mode and Pin Definition Table
Control Bits                    ESAI PINS
SYN TEBE RFSD           SCKR   FSR   HRCK
   0     X        X                SCKR   FSR   HRCK
   1     0        X                F0        F1      F2
    1    1        1                 F0      Trans.  F2
                                                Buffer
                                                Enable


SAICR register bit 8

SAICR Alignment Control (ALC)
The ESAI is designed for 24 bit fractional data, thus shorter data words are left aligned to the MSB (bit 23). Several applications use 16 bit fractional data, thus shorter data words are left aligned to bit 15. Alignment Control (ALC) support this applications. If ALC is set, transmitted and received words are supposed to reside left aligned to bit 15 in the transmit and receive shift registers. If ALC is cleared, transmitted and received word are supposed to reside left align to bit 23 in the transmit and receive shift register.
NOTE While in ALC is set, 20-bit and 24-bit words use are forbidden, and word length should be 8, 12 or 16 bits, otherwise results are unpredictable.


ESAI Register SAISR
ESAI Status Register SAISR

The Status Register (SAISR) is a read-only status register used by the DSP to read the status and serial input flags of the ESAI.

Bit 0-2       IF0-IF2      SAISR Serial Input Flags 0-2

Bits 3-5, 11-12, 18-23 RESERVED
These bits are reserved for future use. They read as zero.

Bit 6         RFS          SAISR Receive Frame Sync Flag

Bit 7         ROE         SAISR Receiver Overrun Error Flag

Bit 8         RDF         SAISR ESAI Receive Data Register Full

Bit 9         REDF       SAISR ESAI Receive Even-Data Register Full

Bit 10       RODF       SAISR ESAI Receive Odd-Data Register Full

Bit 13       TFS          SAISR Transmit Frame Sync Flag

Bit 14       TUE          SAISR Transmitter Underrun Error Flag

Bit 15       TDE          SAISR ESAI Transmit Data Register Empty

Bit 16       TEDE        SAISR ESAI Transmit Even-Data Register Empty

Bit 17       TODE       SAISR ESAI Transmit Odd-Data Register Empty


SAISR register bit  0 to 2
ESAI Register: SAISR  Bit: 0-2 (IF0-IF2)  Serial Input Flag

SAISR Serial Input Flag 0 (IF0) - Bit 0
The ESAI latches data present on the SCKR pin during reception of the first received bit after frame sync is detected. IF0 bit is updated with this data when the receive shift register is transferred into the receive data register. The IF0 bit is enabled only when SCKR is programmed as ESAI in the Port Control Register and SYN is set and RCKD is cleared, indicating that SCKR is an input flag and the synchronous mode is selected; otherwise, IF0 reads as a zero when it is not enabled. Hardware, software, ESAI individual, and STOP reset clear IF0.

SAISR Serial Input Flag 1 (IF1) - Bit 1
The ESAI latches data present on the FSR pin during reception of the first received bit after frame sync is detected. IF1 bit is updated with this data when the receiver shift register is transferred into the receive data register. The IF1 bit is enabled only when FSR is programmed as ESAI in the Port Control Register and SYN is set and RFSD is cleared, indicating that FSR  is an input flag and the synchronous mode is selected; otherwise, IF1 reads as a zero when it is not enabled. Hardware, software, ESAI individual, and STOP reset clear IF1.

SAISR Serial Input Flag 2 (IF2) - Bit 2
The ESAI latches data present on the HCKR pin during reception of the first received bit after frame sync is detected. IF2 bit is updated with this data when the receive shift register is transferred into the receive data register. The IF2 bit is enabled only when HCKR is programmed as ESAI in the Port Control Register and SYN is set and RHCKD is cleared, indicating that HCKR is an input flag and the synchronous mode is selected; otherwise, IF2 reads as a zero when it is not enabled. Hardware, software, ESAI individual, and STOP reset clear IF2.


SAISR register bit  6
ESAI Register: XCTR  Bit:6 (RFS)  Receive Frame Sync Flag

When set, RFS indicates that a receive frame sync occurred during reception of the word in the serial receive data register. This indicates that the data word is from the first time slot in the frame. When RFS is clear and a word is received, it indicates (only in the network mode) that the frame sync did not occur during reception of that word. RFS is cleared by hardware, software, ESAI individual, or STOP reset. RFS is valid only if the receiver is enabled (RE=1).
NOTE In normal mode, RFS will always read as a one when reading data because there is only one time slot per frame – the “frame sync” time
slot.


SAISR register bit  7
ESAI Register: SAISR  Bit: 7 (ROE)  Receiver Overrun Error Flag

This flag is set when the serial receive shift register is filled and ready to transfer to the receiver data register (RX) and RX is already full (i.e., RDF=1). If REIE is set, a DSP receiver overrun error interrupt request will be issued when ROE is set. Hardware, software, ESAI individual, and STOP reset clear ROE. ROE is also cleared by reading the SAISR with ROE set, followed by reading all the enabled receive data registers.


SAISR register bit  8
ESAI Register: SAISR  Bit:8 (RDF)  ESAI Receive Data Register Ful

RDF is set when the contents of the receive shift register are transferred to the receive data register. RDF is cleared when the DSP reads the receive data register or cleared by hardware, software, ESAI individual, or STOP reset. If RIE is set, a DSP receive data interrupt request will be issued


SAISR register bit  9
ESAI Register: SAISR  Bit:9 (REDF)  ESAI Receive Even-Data Register Full

REDF indicates that an even number of receive data transfers have been executed (e.g. second, fourth, etc.). REDF is set when the contents of the receive shift registers are transferred to the receive data registers. REDF is cleared when the DSP reads all the enabled receive data registers or cleared by hardware, software, ESAI individual, or STOP resets. If REDIE is set, a DSP receive even slot data interrupt request will be issued when REDF is set.


SAISR register bit 10
ESAI Register: SAISR  Bit: 10 (RODF)  ESAI Receive Odd-Data Register Full

RODF indicates that an odd number of receive data transfers have been executed (e.g. first, third, etc.). RODF is set when the contents of the receive shift registers are transferred to the receive data registers. RODF is cleared when the DSP reads all the enabled receive data registers or cleared by hardware, software, ESAI individual, or STOP resets.


SAISR register bit 13
ESAI Regsiter: SAISR  Bit: 13 (TFS)   Transmit Frame Sync Flag

When set, TFS indicates that a transmit frame sync occurred in the current time slot. TFS is set at the start of the first time slot in the frame and cleared during all other time slots. Data written to a transmit data register during the time slot when TFS is set will be transmitted (in network mode), if the transmitter is enabled, during the second time slot in the frame. TFS is useful in network mode to identify the start of a frame. TFS is cleared by hardware, software, ESAI individual, or STOP reset. TFS is valid only if at least one transmitter is enabled (TE0, TE1 or TE2 equal 1).
NOTE In normal mode, TFS will always be read as a one when transmitting data because there is only one time slot per frame – the “frame sync” time slot.


SAISR register bit 14
ESAI Register: SAISR  Bit:14 (TUE) Transmitter Underrun Error Flag

TUE is set when at least one of the enabled serial transmit shift registers is empty (no new data to be transmitted) and a transmit time slot occurs. When a transmit underrun error occurs, the previous data (which is still present in the TX registers that were not written) will be retransmitted. In the normal mode, there is only one transmit time slot per frame. In the network mode, there can be up to 32 transmit time slots per frame. If TEIE is set, a DSP transmit underrun error interrupt request will be issued when TUE is set. Hardware, software, ESAI individual, and STOP reset clear TUE. TUE is also cleared by reading the SAISR with TUE set, followed by writing to all the enabled transmit data registers or to TSR.


SAISR register bit 15
ESAI Register: SAISR  Bit: 15 (TDE)  ESAI Transmit Data Register Empty

This flag is set when the contents of the transmit data register of all the enabled transmitters are transferred to the transmit shift register(s); it is also set for a TSR disabled time slot period in network mode (as if data were being transmitted after the TSR was written). When set, TDE indicates that data should be written to all the TX registers of the enabled transmitters or to the time slot register (TSR). TDE is cleared when the DSP writes to all the transmit data registers of the enabled transmitters, or when the DSP writes to the TSR to disable transmission of the next time slot. If TIE is set, a DSP transmit data interrupt request will be issued when TDE is set. Hardware, software, ESAI individual, and STOP reset clear TDE.


SAISR register bit 16
ESAI Register: SAISR Bit:16 (TEDE)  ESAI Transmit Even-Data Register Empty

TEDE indicates that an even number of transmit data transfers have been executed (e.g. second, fourth, etc.). This flag is set when the contents of the transmit data register of all the enabled transmitters are transferred to the transmit shift register(s); it is also set for a TSR disabled time slot period in network mode (as if data were being transmitted after the TSR was written). When set, TEDE indicates that data should be written to all the TX registers of the enabled transmitters or to the time slot register (TSR). TEDE is cleared when the DSP writes to all the transmit data registers of the enabled transmitters, or when the DSP writes to the TSR to disable transmission of the next time slot. If TIE is set, a DSP transmit data interrupt request will be issued when TEDE is set. Hardware, software, ESAI individual, and STOP reset clear TEDE.


SAISR register bit 17
ESAI Register: SAISR Bit:17 (TODE)  ESAI Transmit Odd-Data Register Empty

TODE indicates that an odd number of transmit data transfers have been executed (e.g. second, fourth, etc.). This flag is set when the contents of the transmit data register of all the enabled transmitters are transferred to the transmit shift register(s); it is also set for a TSR disabled time slot period in network mode (as if data were being transmitted after the TSR was written). When set, TODE indicates that data should be written to all the TX registers of the enabled transmitters or to the time slot register (TSR). TODE is cleared when the DSP writes to all the transmit data registers of the enabled transmitters, or when the DSP writes to the TSR to disable transmission of the next time slot. If TIE is set, a DSP transmit data interrupt request will be issued when TODE is set. Hardware, software, ESAI individual, and STOP reset clear TODE.


ESAI Register TSMA and TSMB

Transmit Slot Mask Registers (TSMA, TSMB) are two read/write registers used by the transmitters in network mode to determine for each slot whether to transmit a data word and generate a transmitter empty condition (TDE=1), or to three-state the transmitter data pins.
TSMA and TSMB should be considered as a 32-bit register, TSM. Bit number N in TSM (TS**) is the enable/disable control bit for transmission in slot number N. When bit number N in TSM is cleared, all the transmit data pins of the enabled transmitters are three-stated during transmit time slot number N. The data is still transferred from the Transmit Data Register(s) to the transmit shift register(s) and the Transmit Data Empty flag (TDE) is not set.
Also the Transmitter Underrun Error flag is not set. This means that during a disabled slot, no
Transmitter Empty interrupt is generated. The DSP is interrupted only for enabled slots. Data that
is written to the Transmit Data Register(s) when servicing this request is transmitted in the next
enabled transmit time slot. When bit number N in TSM register is set, the transmit sequence is as usual: data is transferred from TX register(s) to the shift register(s), it is transmitted during slot number N, and TDE flag is set.
Using the slot mask in TSM does not conflict with using TSR. Even if a slot is enabled in TSM,
the user may chose to write to TSR instead of writing to the transmit data registers TXx. This will
cause all the transmit data pins of the enabled transmitters to be three-stated during the next slot.
Data written to the TSM will affect next frame transmission. The frame being transmitted is not
affected by this data and would comply to last TSM setting. Data read from TSM will return last
written data.
After hardware or software reset, the TSM register is preset to $FFFFFFFF, which means that all
32 possible slots are enabled for data transmission.

NOTE: When operating in normal mode, bit 0 of the mask register must be set
to one, otherwise no output will be generated.

Bits 15-0 TS15-TS0
Bits 23-16 RESERVED   read as zero; should be written with zero for future compatibility.


ESAI Register RSMA and RSMB

Receive Slot Mask Registers (RSMA, RSMB) are two read/write registers used by the receiver in network mode to determine for each slot whether to receive a data word and generate a receiver full condition (RDF=1), or to ignore the received data. RSMA and RSMB  should be considered as a 32-bit register, RSM. Bit number N in RSM (RS**) is an enable/disable control bit for receiving data in slot number N.
When bit number N in RSM register is cleared, the data from receive data pin SRD is shifted into the Receive Shift Register during slot number N. The data is not transferred from the Receive Shift Register to the Receive Data Register and the Receiver Data Full flag (RDF) is not set. Also the Receiver Overrun Error flag is not set. This means that during a disabled slot, no Receiver Full interrupt is generated. The DSP is interrupted only for enabled slots.
When bit number N in RSM is set, the receive sequence is as usual: data which is shifted into the receive shift register is transferred to the Receive Data register and RDF flag is set. Data written to the RSM will affect next received frame. The frame being received is not affected by this data and would comply to last RSM setting. Data read from RSM will return last written data.
After hardware or software reset, the RSM register is preset to $FFFFFFFF, which means that all 32 possible slots are enabled for data reception.

NOTE: When operating in normal mode, bit 0 of the mask register must be set to one, otherwise no input will be received.

Bits 15-0   RS15-RS0
Bits 23-16 RESERVED  read as zero; should be written with zero for future compatibility.


ESAI Operating Modes

ESAI operating mode are selected by the ESAI control registers (TCCR, TCR, RCCR, RCR and SAICR). The ESAI has three basic operating modes and many data/operation formats. These modes can be programmed by several bits in the ESAI control registers.

Normal/Network/On-Demand Mode Selection
Selecting between the normal mode and network mode is accomplished by clearing or setting the TMOD0-TMOD1 bits in the TCR register for the transmitter section, and in the RMOD0-RMOD1 bits in the RCR register for the receiver section. For normal mode, the ESAI functions with one data word of I/O per frame (per enabled transmitter or receiver). For the network mode, 2 to 32 time slots per frame may be selected. During each frame, 0 to 32 data words of I/O may be received/transmitted. In either case, the transfers are periodic. The normal mode is typically used to transfer data to/from a single device. Network mode is typically used in time division multiplexed (TDM) networks of codecs or DSPs with multiple words per frame, or multi-channel devices.

Selecting the network mode and setting the frame rate divider to zero (DC=00000) selects the on-demand mode.This special case will not generate a periodic frame sync. A frame sync pulse will be generated only when data is available to transmit. The frame sync signal indicates the first time slot in the frame. The on-demand mode requires that the transmit frame sync be internal (output) and the receive frame sync be external (input). Therefore, for simplex operation, the synchronous mode could be used; however, for full-duplex operation, the asynchronous mode must be used.
Data transmission that is data driven is enabled by writing data into each TX. Although the ESAI is double buffered, only one word can be written to each TX, even if the transmit shift register is empty. The receive and transmit interrupts function as usual using TDE and RDF; however, transmit underruns are impossible for on-demand transmission and are disabled.


ESAI Interrupt Requests

The ESAI can generate eight different interrupt requests (ordered from the highest to the lowest priority):
1. ESAI Receive Data with Exception Status.
Occurs when the receive exception interrupt is enabled (REIE=1 in the RCR register), at least one of the enabled receive data registers is full, and a receiver overrun error has occurred (ROE=1 in the SAISR register). ROE is cleared by first reading the SAISR and then reading one of RX3, RX2, RX1, RX0.

2. ESAI Receive Even-Data
Occurs when the receive even slot data interrupt is enabled (REDIE=1), at least one of the enabled receive data registers is full (RDF=1), the data is from an even slot (REDF=1), and no exception occurred (ROE=0 or REIE=0). Reading all enabled receiver data registers clears RDF and REDF.

3. ESAI Receive Data
Occurs when the receive interrupt is enabled (RIE=1), at least one of the enabled receive data registers is full (RDF=1), no exception occurred (ROE=0 or REIE=0), and no even slot interrupt occurred (REDF=0 or REDIE=0). Reading all enabled receiver data registers clears RDF.

4. ESAI Receive Last Slot Interrupt
Occurs, if enabled (RLIE=1), after the last slot of the frame ended (in network mode only) regardless of the receive mask register setting. The Receive Last slot interrupt may be used for resetting the receive mask slot register, reconfigure the DMA channels and reassignment of data memory pointers. Using the Receive last slot interrupt guarantees that the previous frame was serviced with the previous setting and the new frame will be serviced with the new setting without synchronization problems. Note that the maximum Receive last slot interrupt service time should not exceed N-1 ESAI bits service time (Where N is the number of bits in a slot).

5. ESAI Transmit Data with Exception Status
Occurs when the transmit exception interrupt is enabled (TEIE=1), at least one transmit data register of the enabled transmitters is empty, and a
transmitter underrun error has occurred (TUE=1). TUE is cleared by first reading the SAISR and then writing to all the transmit data registers of the
enabled transmitters, or to the TSR to clear the pending interrupt.

6. ESAI Transmit Last slot interrupt
Occurs, if enabled (TLIE=1), at the start of the last slot of the frame in network mode regardless of the transmit mask register setting. The
Transmit Last slot interrupt may be used for resetting the transmit mask slot register, reconfigure the DMA channels and reassignment of data
memory pointers. Using the Transmit last slot interrupt guarantees that the previous frame was serviced with the previous setting and the new frame
will be serviced with the new setting without synchronization problems. Note that the maximum Transmit last slot interrupt service time should not
exceed N-1 ESAI bits service time (Where N is the number of bits in a slot).

7. ESAI Transmit Even-Data
Occurs when the transmit even slot data interrupt is enabled (TEDIE=1), at least one of the enabled transmit data registers is empty (TDE=1), the
slot is an even slot (TEDE=1), and no exception occurred (TUE=0 or TEIE=0). Writing to all the TX registers of the enabled transmitters, or to the TSR
will clear this interrupt request.

8. ESAI Transmit Data
Occurs when the transmit interrupt is enabled (TIE=1), at least one of the enabled transmit data registers is empty (TDE=1), no exception occurred
(TUE=0 or TEIE=0), and no even slot interrupt occured (TEDE=0 or TEDIE=0). Writing to all the TX registers of the enabled transmitters, or to the TSR
will clear this interrupt request.


GPIO Port C
GPIO (Port C)

The GPIO functionality of the ESAI port is controlled by three registers: Port C Control register (PCRC), Port C Direction register (PRRC) and Port C Data register (PDRC).

Port C Control Register (PCRC)

The read/write 24-bit Port C Control Register (PCRC) in conjunction with the Port C Direction Register (PRRC) controls the functionality of the ESAI GPIO pins. Each of the PC(11:0) bits controls the functionality of the corresponding port pin. See table below for the port pin configurations. Hardware and software reset clear all PCRC bits.
Bits 11-0 PCi, Bits 23-12 RESERVED    i=11,...,0

PDC[i]    PC[i]         Port Pin[i] Function
0              0               disconnected
0              1               GPIO input
1              0               GPIO output
1              1               ESAI                           i=11,...,0

Port C Direction Register (PRRC)

The read/write 24-bit Port C Direction Register (PRRC) in conjunction with the Port C Control Register (PCRC) controls the functionality of the ESAI GPIO pins. Table 4-10 describes the port pin configurations. Hardware and software reset clear all PRRC bits.
Bits 11-0 PDCi, Bits 23-12 RESERVED  i=11,...,0

Port C Data Register (PDRC)

The read/write 24-bit Port C Data Register is used to read or write data to/from ESAI GPIO pins. Bits PD(11:0) are used to read or write data from/to the corresponding port pins if they are configured as GPIO. If a port pin [i] is configured as a GPIO input, then the corresponding PD[i] bit will reflect the value present on this pin. If a port pin [i] is configured as a GPIO output, then the value written into the corresponding PD[i] bit will be reflected on the this pin. Hardware and software reset clears all PDRC bits.
Bits 11-0 PDi, Bits 23-12 RESERVED    i=11,...,0


DAX
Digital Audio Transmitter DAX

Introduction

A block diagram of the DAX

DAX Signals

DAX Interrupt Vectors and Priority

DAX Programming Considerations

DAX Functional Overview

DAX Registers

GPIO (PORT D)


DAX Introduction

The Digital Audio Transmitter (DAX) is a serial audio interface module that outputs digital audio data in the AES/EBU, CP-340 and IEC958 formats. Some of the key features of the DAX are listed below.

 Operates on a frame basis
 Double-buffered audio and non-audio data
 Direct Memory Access
 Programmable clock source
 Supports both Master mode and Slave mode in a digital audio network
 General Purpose I/O

The accessible DAX registers are all mapped in the X I/O memory space. This allows programmers to access the DAX using standard instructions and addressing modes. Interrupts generated by the DAX can be handled with a fast interrupt for cases in which the non-audio data does not change from frame to frame. When the DAX interrupts are disabled, they can still be served by DMA or by a “polling” technique.


DAX block diagram

The shaded registers are directly accessible by DSP instructions.


DAX Signals

The DAX has two signal lines:
 DAX Digital Audio Output (ADO/PD1)—The ADO pin sends audio and non-audio data in the AES/EBU, CP340, and IEC958 formats in a biphase mark format. The ADO pin may also be used as a GPIO pin PD1 if the DAX is not operational.
 DAX Clock Input (ACI/PD0)—When the DAX clock is configured to be supplied externally, the external clock is applied to the ACI pin. The frequency of the external clock must be 256 times, 384 times, or 512 times the audio sampling frequency (256 ´ Fs, 384 ´ Fs, or 512 ´ Fs). The ACI pin may also be used as a GPIO pin PD0 when the DAX is disabled or when operating from the internal DSP clock.


DAX Interrupt Vectors and Priority

DAX Interrupt Vectors
Condition         Address                       Description
XAUR                P:(Base Vector + $0)     DAX Transmit Underrun Error
XADE & XBLK    P:(Base Vector + $2)     DAX Block Transferred
XADE                P:(Base Vector + $6)     DAX Audio Data Register Empty

DAX Interrupt Priority
Priority                      Interrupt
highest                      DAX Transmit Underrun Error
                                 DAX  Block Transferred
lowest                        DAX Audio Data register Empty


DAX Programming Considerations

Initiating A Transmit Session

Audio Data Register Empty Interrupt Handling

Block Transferred Interrupt Handling

DAX Operations with DMA

DAX Operation During STOP


DAX Initiating a Transmit Session

To initiate the DAX operation, follow this procedure:
1. Ensure that the DAX is disabled (PC1 and PC0 bits of Port Control Register PCR remain cleared)
2. Write the non-audio data to the corresponding bits in the XNADR register
3. Write the Channel A and Channel B audio data in the XADR register
4. Write the transmit mode to the XCTR register
5. Enable DAX by setting PC1 bit (and by setting PC0 bit if in slave mode) of Port Control Register PCR; transmission begins


DAX Audio Data Register Empty Interrupt Handling
DAX Audio Data Register Emty Interrupt Handling

When the XDIE bit is set and the DAX is active, an Audio Data register Empty interrupt (XADE = 1) is generated once at the beginning of every frame  transmission. Typically, within an XADE interrupt, the non-audio data bits of the next frame are stored in XNADR and one frame of audio data to be transmitted in the next frame is stored in the FIFO by two consecutive MOVEP instructions to XADR. If non-audio bits are not changed from frame to frame, this procedure can be handled within a fast interrupt routine. Storing the next frame's audio data in the FIFO clears the XADE bit in the XSTR.


DAX Block Transferred Interrupt Handling

An interrupt with the XBLK vector indicates the end of a block transmission and can require some computation to provide the next non-audio data structures that are to be transmitted within the next block. Within the routine, the next audio data can be stored in the FIFO by two consecutive MOVEP instructions to XADR, and the next non-audio data can be stored in the XNADR. XBLK interrupt occurs only if XBIE bit in XCTR is set. If XBIE is clear, a XADE interrupt vector will take place.


DAX Operation with DMA

When working with DMA, XDIE bit of the XCTR must be cleared to avoid XADE interrupt services by the DSP core. The initialization described in "Initiating a Transmit Session" are relevant for operating with DMA. Working with DMA can be done either with or without changing non-audio bit from frame to frame. Table below describes two examples of DMA configuration.

When using DMA, there are two ways of organizing data in memory. Next table shows how to organize data in memory when non-audio data changes from frame to frame, and how to organize it when non-audio data is fixed.

Table: Non-Audio Data bits changes from frame to frame

Table: Non-Audio Data bits do not change from frame to frame


Table NonAudio Data Changes from frame to frame
Table Non-Audio Data Changes from frame to frame

Channel A           $00000A
Non-audio Data    $000009
Channel B           $000008
Channel A           $000007
Non-Audio Data   $000006
Channel B           $000005
Channel A           $000004
Non-audio Data    $000003
Channel B           $000002
Channel A           $000001
Non-Audio Data   $000000


Table NoAudio Data do not Change from Frame to Frame

Channel B         $00000B
Channel A         $00000A
Channel B         $000009
Channel A         $000008
Channel B         $000007
Channel A         $000006
Channel B         $000005
Channel A         $000004
Channel B         $000003
Channel A         $000002
Channel B         $000001
Channel A         $000000


DAX Operation During Stop

The DAX operation cannot continue when the DSP is in the Stop state since no DSP clocks are active. While the DSP is in the Stop state, the DAX will remain in the individual reset state and the status flags are initialized as described for resets. No DAX control bits are affected. It is recommended that the DAX be disabled before the DSP enters the Stop state.


DAX Functional Overview

Description

The DAX consists of:

Control state machine which generates a set of sequencing signals used in the DAX.

Audio Data Register (XADR)

DAX Audio Data Shift Register (XADSR)

Control Register (XCTR)

Non-Audio Data Register (XNADR)

Non-Audio Data Buffer (XNADBUF)

DAX Audio Data Buffers

Biphase Encoder

Preamble Generator

DAX Clock Multiplexer


DAX Functional Overview Description

XADR, XADBUFA, XADBUFB and XADSR creates a FIFO like data path. Channel A is written to XADR and moves to XADBUFA. Then Channel B is written to XADR, and when XADBUFB empties XADR moves into it. XADBUFA moves to the shift register XADSR when XADSR has shifted out its last bit. After Channel A audio and non-audio data has been shifted out, XADBUFB moves into XADSR, and Channel B audio and non audio shift begins.

The frame's non-audio data (stored in XNADR) is transferred to the XADSR (for Channel A) and to the XNADBUF registers (for Channel B) at the beginning of a frame transmission. This is called an “upload.” The DAX Audio Data register Empty (XADE) flag is set when XADR and XADBUFA are empty, and, if Audio Data register Empty interrupt is enabled (XDIE=1), an interrupt request is sent to the DSP core. The interrupt handling routine then send the non-audio data bits to XNADR and the next frame of audio data to XADR (Two sub-frames).

At the beginning of a frame transmission, one of the 8-bit Channel A preambles (Z-preamble for the first sub-frame in a block, or X-preamble otherwise) is generated in the preamble generator, and then shifted out to the ADO pin in the first eight time slots. The preamble is generated in biphase mark format. The twenty-four audio and three non-audio data bits in the XADSR are shifted out to the biphase encoder, which shifts them out through the ADO pin in the biphase mark format in the next fifty-four time slots. The parity generator calculates an even parity over the 27 bits of audio and non-audio data, and then outputs the result through the biphase encoder to the ADO pin at the last two time slots. This is the end of the first (Channel A) sub-frame transmission.

The second sub-frame transmission (Channel B) starts with the preamble generator generating the Channel B preamble (Y-preamble). At the same time, Channel B audio and non-audio data is transferred to the XADSR shift-register from the XADBUFB and XNADBUF registers. The generated Y-preamble is output immediately after the Channel A parity and is followed by the audio and non-audio data in the XADSR, which is in turn followed by the calculated parity for Channel B. This completes a frame transmission. When the Channel B parity is sent, the audio data for the next frame, stored in XADBUFA and the non-audio data bits from the XNADR, are uploaded to XADSR.


DAX register XADR

DAX Audio Data Register (XADR)
X:(Base Address + $2) or X:(Base Address + $3)
XADR is a 24-bit write-only register. One frame of audio data, which is to be transmitted in the next frame slot, is transferred to this register. Successive write accesses to this register will store Channel A and Channel B alternately in XADBUFA and in XADBUFB respectively. When XADR and XADBUFA are empty, XADE bit in the XSTR is set, and, if Audio Data Register Empty interrupt is enabled (XDIE=1), an interrupt request is sent to the DSP core. When Channel B is transferred to XADR, the XADE bit in the XSTR is cleared. XADR can also be accessed by DMA. When XADR and XADBUFA are empty, the DAX sends a DMA request to the core. The DMA transfers non-audio data bits to XNADR (optional), and after that Channel A and Channel B to XADR. The XADR can be accessed with two different successive addresses. This feature supports sending non-audio data bits, Channel A and Channel B to DAX in three successive DMA transfers.


DAX register XADSR
DAX Audio Data Shift Register (XADSR)

DAX Audio Data Shift Register (XADSR)
The XADSR is a 27-bit shift register that shifts the 24-bit audio data and the 3-bit non-audio data for one sub-frame. The contents of XADBUFA or XADBUFB are directly transferred to the XADSR at the beginning of the sub-frame transmission. At the time Channel A sub-frame is being transferred to XADSR, the three bits of non-audio data (V-bit, U-bit and C-bit) for Channel A in the DAX non-audio data register (XNADR) are transferred to the three highest-order bits of the XADSR. At the beginning of the Channel B transmission, audio and non-audio data for Channel B is transferred from the XADBUFB and the XNADBUF to the XADSR for shifting. The data in the XADSR is shifted toward the lowest-order bit at the fifth to thirty-first bit slot of each sub-frame transmission. This register is not directly accessible by DSP instructions.


DAX register XCTR

DAX Control Register (XCTR) is a 24-bit read/write register that controls the DAX operation.

Bit 0        XDIE      Audio Data Register Empty Interrupt Enable

Bit 1        XUIE      Underrun Error Interrupt Enable

Bit 2       XBIE       Block Transferred Interrupt Enable

Bits 3,4  XCS[1:0] DAX Clock Input Select

Bit 5      XSB        DAX Start Block

Bits 0, 5-9, 16-23  RESERVED


XCTR register bit 0
DAX  Register: XCTR   Bit: 0 ( XDIE)  Audio Data Register Empty Interrupt Enable

When the XDIE bit is set, the Audio Data register Empty interrupt is enabled and sends an interrupt request signal to the DSP if the XADE status bit is set. When XDIE bit is cleared, this interrupt is disabled.
Note: This bit is cleared by software reset and hardware reset.


XCTR register bit 1
DAX Register: XCTR  Bit: 1 (XUIE)   Underrun Error Interrupt Enable

When the XUIE bit is set, the Underrun Error interrupt is enabled and sends an interrupt request signal to the DSP if the XAUR status bit is set. When XUIE bit is cleared, this interrupt is disabled.
Note: This bit is cleared by software reset and hardware reset.


XCTR register bit 2
DAX Register: XCTR  Bit:2 (XBIE)  Block Transferred Interrupt Enable

When the XBIE bit is set, the Block Transferred interrupt is enabled and sends an interrupt request signal to the DSP if the XBLK and XADE status bits are set. When XBIE bit is cleared, this interrupt is disabled.
Note: This bit is cleared by software reset and hardware reset.


XCTR register bit 3 and 4
DAX Register: XCTR  Bit: 3 and 4 (XCS[1:0])  DAX Clock Input Select

The XCS[1:0] bits select the source of the DAX clock and/or its frequency. Table below shows the configurations selected by these bits. These bits should be changed only when the DAX is disabled.
The XCS bits are cleared by software reset and hardware reset.

Clock Source Selection Table

XCS1 XCS0        DAX Clock Source
  0       0            DSP Core Clock (f = 1024 x fs)
  0       1            ACI Pin, f = 256 x fs
  1       0            ACI Pin, f = 384 x fs
  1       1            ACI Pin, f = 512 x fs


XCTR register bit 5
DAX Register: XCTR  Bit: 5 (XSB)  DAX Start Block

The XSB bit forces the DAX to start a new block. When this bit is set, the next frame will start with “Z” preamble and will start a new block even though the current block was not finished.
Note: This bit is cleared when the new block starts. It is also cleared by software reset and hardware reset.


DAX register XNADR
DAX Non-Audio Data Register (XNADR)

DAX Non-Audio Data Register (XNADR)        X:(Base Address + $1)
The XNADR is a 24-bit write-only register. It holds the three bits of non-audio data for each sub-frame. XNADR can be accessed by core instructions or by DMA.

Bits 23-16, 9-0  RESERVED

Bit 10   XVA   DAX Channel A Validity

Bit 11   XUA   DAX Channel A User Data

Bit 12   XCA   DAX Channel A Channel Status

Bit 13   XVB   DAX Channel B Validity

Bit 14   XUB   DAX Channel B User Data

Bit 15   XCB   DAX Channel B Channel Status


XNADR register bit 10
DAX Register: XNADR  Bit:10 (XVA) DAX Channel A Validity

The value of the XVA bit is transmitted as the twenty-ninth bit (Bit 28) of Channel A sub-frame in the next frame.
Note: This bit is not affected by any of the DAX reset states.


XNADR register bit 11
DAX Register: XNADR  Bit:11(XUA)  DAX Channel A User Data

The value of the XUA bit is transmitted as the thirtieth bit (Bit 29) of the Channel A sub-frame in the next frame.
Note: This bit is not affected by any of the DAX reset states.


XNADR register bit 12
DAX Register: XNADR  Bit:12 (XCA)   DAX Channel A Channel Status

The value of the XCA bit is transmitted as the thirty-first bit (Bit 30) of the Channel A sub-frame in the next frame.
Note: This bit is not affected by any of the DAX reset states.


XNADR register bit 13
DAX REgister: XNADR  Bit:13(XVB)  DAX Channel B Validity

The value of the XVB bit is transmitted as the twenty-ninth bit (Bit 28) of the Channel B sub-frame in the next frame.
Note: This bit is not affected by any of the DAX reset states.


XNADR register bit 14
DAX Register: XNADR  Bit:14 (XUB)  DAX Channel B User Data

The value of the XUB bit is transmitted as the thirtieth bit (Bit 29) of the Channel B sub-frame in the next frame.
Note: This bit is not affected by any of the DAX reset states.


XNADR register bit 15
DAX Register: XNADR  Bit:15(XCB)  DAX Channel B Channel Status

The value of the XCB bit is transmitted as the thirty-first bit (Bit 30) of the Channel B sub-frame in the next frame.
Note: This bit is not affected by any of the DAX reset states.


DAX Non Audio Data Buffer XNADBUF
DAX Non-Audio Data Buffer XNADBUF

The XNADBUF is a 3-bit register that temporarily holds Channel B non-audio data (XVB, XUB and XCB) for the current transmission while the Channel A data is being transmitted. This mechanism provides programmers more instruction cycles to store the next frame's non-audio data to the XCB, XUB, XVB, XCA, XUA and XVA bits in the XNADR. The data in the XNADBUF register is transferred to the XADSR along with the contents of the XADBUF register at the beginning of Channel B transmission.
Note: The XNADBUF register is not directly accessible by DSP instructions.


DAX Audio Data Buffers

DAX Audio Data Buffers (XADBUFA / XADBUFB)
XADBUFA and XADBUFB are 24-bit registers that buffer XADR from XADSR, creating a FIFO like data path. These registers hold the next two sub-frames of audio data to be transmitted. Channel A audio data is transferred from XADR to XADBUFA if XADBUFA is empty. Channel B audio data is transferred from XADR to XADBUFB if XADBUFB is empty. Audio data is transferred from XADBUFA and XADBUFB alternately to XADSR if XADSR shifted out all the audio and non audio bits of the currently transmitted channel. This buffering mechanism provides more cycles to write the next audio data to XADR. These registers are not directly accessible by DSP instructions.


DAX Biphase Encoder

The DAX biphase encoder encodes each audio and non-audio bit into its biphase mark format, and shifts this encoded data out to the ADO output pin synchronous to the biphase clock.


DAX Preamble Generator

The DAX preamble generator automatically generates one of three preambles in the 8-bit preamble shift register at the beginning of each sub-frame transmission, and shifts it out. The generated preambles always start with “0”. Bit patterns of preambles generated in the preamble generator are shown in table below. The preamble bits are already in the biphase mark format.

There is no programmable control for the preamble selection. The first sub-frame to be transmitted (immediately after the DAX is enabled) is the beginning of a block, and therefore it has a “Z” preamble. This is followed by the second sub-frame, which has an “Y” preamble. After that, “X” and “Y” preambles are transmitted alternately until the end of the block transfer (192 frames transmitted). See Figurebelow for an illustration of the preamble sequence.

Preamble Bit Patterns Table
Preamble   Bit Pattern    Channel
X               00011101     A
Y               00011011     B
Z               00010111     A (first in block)

Note: For proper operation of the DAX, the DSP core clock frequency must be at least five times higher than the DAX bit shift clock frequency (64 ´ Fs).


DAX Clock Multiplexer

The DAX clock multiplexer selects one of the clock sources and generates the biphase clock (128 ´ Fs) and shift clock (64 ´ Fs). The clock source can be selected from the following options (see also XCS bits(3,4) of XCTR register).
 The internal DSP core clock—assumes 1024 ´ Fs
 DAX clock input pin(ACI)—512 ´ Fs
 DAX clock input pin(ACI)—384 ´ Fs
 DAX clock input pin(ACI)—256 ´ Fs

Note: For proper operation of the DAX, the DSP core clock frequency must be at least five times higher than the DAX bit shift clock frequency (64 ´ Fs).


DAX Registers
DAX Registers Accessible by DSP instructions

XADR - Audio Data Register

XCTR - Control Register

XNADR - Non-Audio Data Register

XSTR - Status Register


DAX register XSTR
DAX Status Register XSTR

DAX Status Register (XSTR) is a 24-bit read-only register that contains the DAX status flags.

Bit 0      XADE   DAX Audio Data Register Empty

Bit 1      XAUR   DAX Transmit Underrun Error Flag

Bit 2      XBLK   DAX Block Transfer Flag

Bits 23-3   RESERVED


XSTR register bit 0
DAX Register: XSTR  Bit:0 (XADE)  DAX Audio Data Register Empty

The XADE status flag indicates that the DAX audio data register XADR and the audio data buffer XADBUFA are empty (and ready to receive the next frame's audio data). This bit is set at the beginning of every frame transmission (more precisely, when Channel A audio data is transferred from XADBUFA to XADSR). When XADE is set and the interrupt is enabled (XDIE = 1), an Audio Data Register Empty interrupt request with its interrupt vector is sent to the DSP core.
Note: XADE is cleared by writing two channels of audio data to XADR. It is also cleared by software reset and hardware reset, and by the Stop state.


XSTR register bit 1
DAX Register: XSTR  Bit: 1 (XAUR)  DAX Transmit Underrun Error Flag

The XAUR status flag is set when the DAX audio data buffers XADBUFA or XADBUFB are empty and the respective audio data upload occurs. When a DAX underrun error occurs, the previous frame data will be re-transmitted in both channels. When XAUR is set and the interrupt is enabled (XUIE = 1), an Underrun Error interrupt request with its interrupt vector is sent to the DSP core. This allows programmers to write an exception handling routine for this special case.
Note: The XAUR bit is cleared by reading the XSTR register with XAUR set, followed by writing two channels of audio data to XADR. It is also cleared by software reset and hardware reset, and by the Stop state.


XSTR register bit 2
DAX Register: XSTR  Bit:2 (XBLK) DAX Block Transfer Flag

The XBLK flag indicates that the frame being transmitted is the last frame in a block. This bit is set at the beginning of the transmission of the last frame (the 191st frame). This bit does not cause any interrupt. However, if XBIE=1 it causes a change in the interrupt vector sent to DSP core in the event of an Audio Data register Empty interrupt, so that a different interrupt routine can be called (providing the next non-audio data structures for the next block as well as storing audio data for the next frame). Writing two channels of audio data to XADR clears this bit.
Note: Software reset, hardware reset, and the Stop state clear XBLK.


GPIO Port D
GPIO (Port D)

Port D Control Register (PCRD)

Port D Direction Register (PRRD)

Port D Data Register (PDRD)


DAX GPIO register PCDR

The read/write 24-bit DAX Port GPIO Control Register controls the functionality of DAX GPIO pins. Each of PC(1:0) bits controls the functionality of the corresponding port pin. When a PC[i] bit is set, the corresponding port pin is configured as a DAX pin. When a PC[i] bit is cleared, the corresponding port pin is configured as GPIO pin. If both PC1 and PC0 are cleared, DAX is disabled. Hardware and software reset clear all PCRD bits.

Bit 1-0   PC1-PC0  Port Control Bits; 1-DAX, 0-GPIO
Bits 23-2 RESERVED


DAX GPIO register PRRD

The read/write 24 bit Port Direction Register controls the direction of DAX GPIO pins. When port pin[i] is configured as GPIO, PDC[i] controls the port pin direction. When PDC[i] is set, the GPIO port pin[i] is configured as output. When PDC[i] is cleared the GPIO port pin[i] is configured as input. Hardware and software reset clear all PRRD bits.

Bit1- 0    PDC1-PDC0    Direction Control Bits, 1-Output, 0-Input
Bits 23-2 RESERVED


DAX GPIO register PDRD

Port D Data Register
The read/write 24 bit Port D Data Register is used to read or write data to/from DAX GPIO pins. Bits PD(1:0) are used to read or write data from/to the corresponding port pins if they are configured as GPIO. If a port pin [i] is configured as a GPIO input, then the corresponding PD[i] bit will reflect the value present on this pin. If a port pin [i] is configured as a GPIO output, then the value written into the corresponding PD[i] bit will be reflected on the this pin. Hardware and software reset clear all PDRD bits.

Bits 1-0     D1-PD0
Bits 23-2   RESERVED


Triple Timer Module

Introduction

Registers

Triple  Timer Module Block Diagram

Triple Timer Operating Modes


Triple Timer Module Introduction
Triple Timer Module

This is a peripheral module for the DSP56300 core family  composed of a common 21-bit prescaler and three independent and identical general purpose 24-bit timer/event counters, each one having its own register set.

Each timer can use internal or external clocking and can interrupt the DSP after a specified number of events (clocks). Timer 0 can signal an external device after counting internal events. Each timer can also be used to trigger DMA transfers after a specified number of events (clocks) occurred. One timer (Timer 0) connects to the external world through one bidirectional pin TIO0. When TIO0 is configured as input, the timer functions as an external event counter or can measure external pulse width/signal period. When TIO0 is used as output the timer is functioning as either a timer, a watchdog or a Pulse Width Modulator. When the TIO0 pin is not used by the timer it can be used as a General Purpose Input/Output Pin.


Triple Timer Module Registers

Timer Registers:

TCRx      Timer Count Register for timer x

TLRx      Timer Load Register for timer x

TCPRx   Timer Compare Register for timer x

TCSRx   Timer Control/Status Register for timer x

Prescaler is a 21-bit counter which is decremented on each rising edge of the prescaler input clock. The counter is enabled when at least one of the three timers is both enabled (TE i=1) and using the prescaler output as its source (PCE i=1).
Prescaler Registers:

TPLR     Timer Prescaler Load Register

TPCR     Timer Prescaler Count Register


Triple Timer register TCR
Timer Count Register TCR

The Count Register is a 24-bit read-only Register (TCR). In Timer and Watchdog Modes the counter contents can be read at any time by reading the TCR register. In Measurement Modes the TCR will be loaded with the current value of the counter on the appropriate edge of the input signal and its value can be read to determine the width, period or delay of leading edge of the input signal (incoming on the TIO0 pin).


Triple Timer register TLR
Timer Load Register TLR

The Load Register is a 24-bit write-only Register (TLR). In all modes the counter is preloaded with the TLR value after the Timer Enable bit is set (TE=1) and a first event occurs.
In Timer Modes, if timer reload mode is set (TRM=1), the counter is reloaded each time after it has reached the value contained by the Timer Compare Register and the new event occurs.
In Measurement Modes, if timer reload mode is set (TRM=1), the counter is reloaded with the TLR value on each appropriate edge of the input signal, after the Timer Enable bit is set (TE=1).
In PWM Modes, if timer reload mode is set (TRM=1), the counter is reloaded each time after it has overflowed and the new event occurs.
In Watchdog Modes, if timer reload mode is set (TRM=1), the counter is reloaded each time after it has reached the value contained by the Timer Compare Register and the new event occurs. In this mode, the counter is also reloaded whenever the TLR is written with a new value while the Timer Enable bit is set (TE = 1).
In all modes, if TRM is cleared (TRM=0), the counter operates as free running counter.


Triple Timer register TCPR
Timer Compare Register TCPR

The compare register is a 24-bit read-write register which contains the value to be compared to the counter value. The counter value is compared against the value contained by the TCPR on every timer clock after the Timer Enable bit is set (TE=1). When the compare matches, the TCF bit is set and, if interrupts are enabled (TCIE=1), an interrupt is generated. In Measurement Modes the TCPR is ignored.


Triple Timer register TCSR
Timer Control/Status Register TCSR

The control/status register is a 24-bit read/write register that controls the timer and reflects its status.

Timer Enable (TE) Bit 0

Timer Overflow Interrupt Enable (TOIE) Bit 1

Timer Compare Interrupt Enable (TCIE) Bit 2

Bit 3 10, 14, 16-19, 22, 23     RESERVED

Timer Control (TC0-TC3) Bits 4-7

Timer Control (TC0-TC3) Tables

Inverter (INV) Bit 8

Timer reload mode (TRM) Bit 9

Direction (DIR) Bit 11

Data Input (DI) Bit 12

Data Output (DO) Bit 13

Prescaled Clock Enable (PCE) Bit 15

Timer Overflow Flag (TOF) Bit 20

Timer Compare Flag (TCF) Bit 21


TCSR register bit  0
Triple Timer Register: TCSR  Bit: 0 (TE)  Timer Enable

This bit  is used to enable or disable the timer. Setting the TE bit (TE=1) will enable the timer and clear the timer counter. The counter will start counting according to the mode defined by TC3-TC0. Clearing the TE bit will disable the timer. TE is cleared by hardware RESET and software RESET (RESET instruction).
Note: When all the three timers are disabled and not in GPIO mode, the TIO0 pin becomes tri-state. In order to prevent undesired spikes on the TIO0 pin (when switching from tri-state into active state) it is recommended to use external an pull-up or pull down resistor tied to the TIO0 pin.


TCSR register bit  1
Triple Timer Register: TCSR  Bit: 1 (TOIE)  Timer Overflow Interrupt Enable

This bit is used to enable the timer overflow interrupts. The overflow interrupt will be generated after the counter wraparound occurred, i.e. the counter value has changed from $FFFFFF to $000000 when a new event occurred. Setting TOIE (TOIE=1) will enable the overflow interrupts. When the bit is cleared (TOIE=0) the overflow interrupts are disabled. TOIE is cleared by hardware RESET and software RESET (RESET instruction).


TCSR register bit  2
Triple Timer Register: TCSR  Bit: 2 (CIE) Timer Compare Interrupt Enable

This bit is used to enable the timer compare interrupts. The compare interrupt will be generated after the counter matches the compare register (in the Timer, PWM or Watchdog Modes). If TCPR is loaded with N, an interrupt will occur after (N-M+1) events, where M is TLR value. Setting TCIE (TCIE=1) will enable the compare interrupts. When the bit is cleared (TCIE=0) the compare interrupts are disabled. TCIE is cleared by hardware RESET and software RESET (RESET instruction).


TCSR register bit  4 to 7
Triple Timer Register: TCSR  Bit: 4 to 7 (TC0-TC3) Timer Control

These bits control the source of the timer clock, the behavior of the TIO0 pin and  the timer mode of operation. TC0-TC3 bits are cleared by hardware RESET and software RESET (RESET instruction).
Note: If the clock is external, the counter will be incremented by the transitions on the TIO0 pin. The external clock is internally synchronized to the internal clock and
its frequency should be lower than the internal operating frequency divided by 4
(CLK/4).
Note: The TC3-TC0 bits should be changed only when TE=0 (i.e. timer disabled) to ensure proper functionality.
See also: TCSR register bits 4 to 7 tables


TCSR register bit  4 to 7 tables
Timer Control Bits for Timer 0
TC3- TC0               TIO0         CLOCK     MODE
   0 0 0 0                 GPIO *     Internal       Timer and GPIO
   0 0 0 1                 Output      Internal       Timer Pulse
   0 0 1 0                 Output      Internal       Timer Toggle
   0 0 1 1                  Input        External      Event Counter
   0 1 0 0                  Input        Internal        Input Width
   0 1 0 1                  Input        Internal        Input Period
   0 1 1 0                  Input        Internal        Capture
   0 1 1 1                  Output    Internal         Pulse Width Modulation (PWM)
   1 0 0 0                  -                      -            Reserved
   1 0 0 1                 Output     Internal         Watchdog Pulse
   1 0 1 0                 Output     Internal         Watchdog Toggle
   1 0 1 1                 -                       -            Reserved
   1 1  x  x                -                       -            Reserved
* the GPIO function is enabled only if TC3-TC0 are all 0 (zero)

Timer Control Bits for Timers 1 and 2
TC3-TC0        CLOCK            MODE
   0 0 0 0          Internal            Timer
   0 0 0 1               -                  Reserved
   0 0 1X                -                 Reserved
   0 1XX                -                  Reserved
   1 XXX               -                  Reserved


TCSR register bit  8
Triple Timer Register: TCSR  Bit: 8 (INV) Inverter

Inverter Bit  affects the polarity of the external incoming signal on the TIO0 pin (when TIO0 is programmed as input) and affects the polarity of the pulse generated on the TIO0 pin (when TIO0 is programmed as output). In the Timer Modes if TIO0 is programmed as input and INV=0, the 0 to 1 transitions on the TIO0 input pin will increment the counter; if INV=1, the 1 to 0 transitions on the TIO0 input pin will increment the counter. In the Input Width Mode the INV bit determines whether the high pulse or the low pulse is measured and in the Input Period Mode the INV bit determines whether the period is measured between rising or falling edges. If TIO0 is programmed as output and INV=0, the pulse generated by the timer will be of positive polarity; if INV=1, the pulse generated by the timer will be inverted. INV is cleared by hardware RESET and software RESET (RESET instruction). This bit is not in use for Timers 1 and 2. It should be left cleared.
Note: The INV bit affects both the timer and the GPIO modes of operation.
Note: The INV bit should be changed only when TE=0 (i.e. timer disabled), or in GPIO mode of operation, to ensure proper functionality.
Note: The polarity of the prescaler source clock, when TIO0 is used as input to the prescaler, is not affected by the corresponding INV bit.


TCSR register bit  9
Triple Timer Register: TCSR  Bit:9 (TRM) Timer Reload Mode

Timer reload mode controls the counter preload operation. In Timer and Watchdog Modes the counter is preloaded with the TLR value after the Timer Enable bit is set (TE=1) and a first event occurs. If timer reload mode is set (TRM=1), the counter is reloaded each time after it has reached the value contained by the Timer Compare Register and the new event occurs. In PWM Mode the counter is reloaded each time counter wraparound has occurred (overflow) and the new event occurs. In Measurement Modes the counter is preloaded
with the TLR value (if TRM=1) on each appropriate edge of the input signal, after the Timer Enable bit is set (TE=1). If TRM is cleared (TRM=0), the counter operates as free running counter, incrementing on each incoming event. TRM is cleared by hardware RESET and software RESET (RESET instruction).


TCSR register bit 11
Triple Timer Register: TCSR  Bit: 11 (DIR)  Direction Bit

This bit determines the behavior of the TIO0 pin when used as general purpose Input/Output pin. When DIR=0 the TIO0 pin is an input and when DIR=1 the TIO0 pin is an output. The TIO0 pin can be used as a general purpose Input/Output (GPIO) pin only when TC3-TC0 are all zero. If one of TC3, TC2, TC1 or TC0 is not 0 the GPIO function is disabled and the DIR pin has no effect. DIR is cleared by hardware RESET and software RESET (RESET instruction). This bit is not in use for Timers 1 and 2. It should be left cleared.


TCSR register bit 12
Triple Timer Register: TCSR  Bit:12 (DI) Data Input

This bit reflects the value of TIO0 pin according to the INV bit. Reading the DI bit will read the TIO0 pin if INV=0, or the inverted TIO0 pin if INV=1.


TCSR register bit 13
Triple Timer Register: TCSR  Bit:13 (DO) Data Output

When the GPIO mode is enabled (TC3-TC0 are all zero) and DIR=1 the TIO0 pin acts as data output. Writing the DO bit will write the data to the TIO0 pin. If the INV bit is set the data on the TIO0 pin will be inverted. When GPIO mode is disabled writing the DO bit will have no effect. DO is cleared by hardware RESET and software RESET (RESET instruction). This bit is not in use for Timers 1 and 2. It should be left cleared.


TCSR register bit 15
Triple Timer Register:TCSR  Bit:15 (PCE)  Prescaled Clock Enable

This bit is used to select the prescaled clock as the timer source clock. When PCE is cleared the timer uses either internal (CLK/2) or external (TIO0) source clock as determined by the timer operating mode. When PCE is set the prescaler output is used as the timer source clock for the counter regardless of the timer operating mode. PCE is cleared by hardware RESET and software RESET (RESET instruction).
Note: The PCE bit should be changed only when TE=0 (i.e. timer disabled) to ensure proper functionality.
Note: The source clock for the prescaler is determined only by the Prescaler Source bits (PS0-PS1) of the Timer Prescaler Load Register (TPLR). Therefore Timers 1 and 2 may be clocked by prescaled clock derived from the TIO0 pin.


TCSR register bit 20
Triple Timer Register: TCSR  Bit: 20 (TOF)  Timer Overflow Flag

Timer Overflow Flag  when set indicates that counter wraparound has occurred. The Timer Overflow Flag bit is cleared when writing a one into the TOF bit. Writing a zero into the TOF bit has no effect. The bit is cleared also when the timer overflow interrupt is serviced (timer overflow interrupt acknowledge). TOF is cleared by hardware RESET, software RESET (RESET instruction), STOP instruction and also by the timer disabling (TE=0).


TCSR register bit 21
Triple Timer Register: TCSR  Bit: 21 (TCF)  Timer Compare Flag

In the Timer, PWM and Watchdog Modes the Timer Compare Flag bit when set indicates that (N-M+1) events are counted, where N is the value in the compare register and M is TLR value. In the Measurement Modes the TCF bit when set indicates that the measurement has been completed. The Timer Compare Flag bit is cleared when writing a one into the TCF bit. Writing a zero into the TCF bit has no effect. The bit is cleared also when the timer compare interrupt is serviced (timer compare interrupt acknowledge). TCF is cleared by hardware RESET, software RESET (RESET instruction), STOP instruction and also by the timer disabling (TE=0). Note: TOF and TCF status bits are cleared by writing one to the specific bit. In order to assure that only the desired bit is cleared, the programmer should not use the BSET command. The proper way to clear these bits is to write (MOVE(P) instruction) one to the flag to be cleared and zero to the other flag.


Triple Timer register TPLR
TPLR - Timer Prescaler Load Register

The Timer Prescaler Load Register is a 24-bit read/write register that controls the prescaler divide factor and the source for the prescaler input clock.

Bit 23         RESERVED
Bits 0-20    PL0 - PL20    Prescaler Preload Value

These 21 bits contain the prescaler preload value. This preload value is loaded into the prescaler counter whenever either the counter reaches the value of zero or the counter switches state from disabled to enabled. If PL0-PL20 = N then the prescaler will count N+1 source clock cycles before generating a prescaled clock pulse. Therefore the prescaler divide factor is preload value + 1. PL0-PL20 bits are cleared by hardware !RESET and software RESET (RESET instruction).

Bits 21, 22   PPS0, PS1 Prescaler Source

The two Prescaler Source bits control the source of the prescaler clock. Table below summarizes the functionality of the PS bits. The internal clock CLK/2 (the DSP clock divided by two) is selected when bits PS0-PS1 are cleared.
PS0-PS1 bits are cleared by hardware !RESET and software RESET (RESET instruction).

PS1    PS0     PRESCALER CLOCK SOURCE
  0         0         Internal CLK/2
  0         1         TIO0
  1         0         Reserved
  1         1         Reserved


Triple Timer register TPCR
TimerPrescaler Count Register TPCR

The Timer Prescaler Count Register is a 24-bit read only register that reflects the current value in the prescaler counter.

Bits 21,22,23    RESERVED
Bits 0-20           PC0-PC20   Prescaler Counter Value
These 21 bits contain the current value in the prescaler counter.


Triple Timer Block Diagram


Triple Timer Operating Modes

Timer Modes
Timer mode, internal clock, no output (mode 0)
Timer mode, internal clock, output pulse enable (mode 1)
Timer mode, internal clock, output toggle enable (mode 2)
Timer mode, external clock, event counter (mode 3)
Measurement Modes
Pulse width measurement mode (mode 4)
Period measurement mode (mode 5)
Capture mode (mode 6)
PWM Modes
Pulse Width Modulation mode, internal clock, output toggle enable (mode 7)
Watchdog Modes
Watchdog mode, internal clock, output pulse enable (mode 9)
Watchdog mode, internal clock, output toggle enable (mode 10)
Reserved Modes
Modes 8,11,12,13,14 and 15 are reserved.


Internal IO Memory Map
INTERNAL I/O Memory Map

The DSP56362 on-chip peripheral modules have their register files programmed to the addresses in the internal X-I/O memory range (the top 128 locations of the X data memory space) as shown:

IPR
IPR-C     $FFFFFF       INTERRUPT PRIORITY REGISTER CORE
IPR-P     $FFFFFE      INTERRUPT PRIORITY REGISTER PERIPHERAL

PLL
PCTL     $FFFFFD        PLL CONTROL REGISTER

ONCE
 OGDB    $FFFFFC       ONCE GDB REGISTER

BIU
BCR       $FFFFFB        BUS CONTROL REGISTER
DCR       $FFFFFA        DRAM CONTROL REGISTER
AAR0     $FFFFF9        ADDRESS ATTRIBUTE REGISTER 0
AAR1     $FFFFF8        ADDRESS ATTRIBUTE REGISTER 1
AAR2     $FFFFF7        ADDRESS ATTRIBUTE REGISTER 2
AAR3     $FFFFF6        ADDRESS ATTRIBUTE REGISTER 3
IDR        $FFFFF5         ID REGISTER

DMA
DSTR     $FFFFF4         DMA STATUS REGISTER
DOR0     $FFFFF3         DMA OFFSET REGISTER 0
DOR1     $FFFFF2         DMA OFFSET REGISTER 1
DOR2     $FFFFF1         DMA OFFSET REGISTER 2
DOR3     $FFFFF0         DMA OFFSET REGISTER 3

DMA0, DMA1, DMA2, DMA3, MA4, DMA5
DMA Source Address Registers:

DSR0       $FFFFEF
DSR1       $FFFFEB
DSR2       $FFFFE7
DSR3       $FFFFE3
DSR4       $FFFFDF
DSR5       $FFFFDB

DMA Destination Address Registers:

DDR0       $FFFFEE
DDR1       $FFFFEA
DDR2       $FFFFE6
DDR3       $FFFFE2
DDR4       $FFFFDE
DDR5       $FFFFDA

DMA Counters

DCO0      $FFFFED
DCO1      $FFFFE9
DCO2      $FFFFE5
DCO3      $FFFFE1
DCO4      $FFFFDD
DCO5      $FFFFD9

DMA Control Registers

DCR0       $FFFFEC
DCR1       $FFFFE8
DCR2       $FFFFE4
DCR3       $FFFFE0
DCR4       $FFFFDC
DCR5       $FFFFD8

PORT D
PCRD       $FFFFD7     PORT D CONTROL REGISTER
PRRD       $FFFFD6     PORT D DIRECTION REGISTER
PDRD       $FFFFD5     PORT D DATA REGISTER

DAX
XSTR        $FFFFD4    DAX STATUS REGISTER
XADRB     $FFFFD3    DAX AUDIO DATA REGISTER B
XADRA     $FFFFD2    DAX AUDIO DATA REGISTER A
XNADR     $FFFFD1    DAX NON-AUDIO DATA REGISTER
XCTR        $FFFFD0    DAX CONTROL REGISTER
                $FFFFCF    RESERVED
                $FFFFCE    RESERVED
                $FFFFCD    RESERVED
                $FFFFCC    RESERVED
                $FFFFCB    RESERVED
                $FFFFCA    RESERVED

PORT B
HDR         $FFFFC9    HOST PORT GPIO DATA REGISTER
HDDR       $FFFFC8    HOST PORT GPIO DIRECTION REGISTER

HDI08
HOTX       $FFFFC7    HOST TRANSMIT REGISTER
HORX      $FFFFC6    HOST RECEIVE REGISTER
HBAR      $FFFFC5    HOST BASE ADDRESS REGISTER
HPCR      $FFFFC4    HOST PORT CONTROL REGISTER
HSR        $FFFFC3     HOST STATUS REGISTER
HCR        $FFFFC2     HOST CONTROL REGISTER
               $FFFFC1     RESERVED
               $FFFFC0     RESERVED

PORT C
PCRC       $FFFFBF   PORT C CONTROL REGISTER
PRRC       $FFFFBE   PORT C DIRECTION REGISTER
PDRC       $FFFFBD   PORT C GPIO DATA REGISTER

ESAI
RSMB       $FFFFBC   ESAI RECEIVE SLOT MASK REGISTER B
RSMA       $FFFFBB   ESAI RECEIVE SLOT MASK REGISTER A
TSMB        $FFFFBA   ESAI TRANSMIT SLOT MASK REGISTER B
TSMA        $FFFFB9   ESAI TRANSMIT SLOT MASK REGISTER A
RCCR        $FFFFB8   ESAI RECEIVE CLOCK CONTROL REGISTER
RCR          $FFFFB7   ESAI RECEIVE CONTROL REGISTER
TCCR        $FFFFB6   ESAI TRANSMIT CLOCK CONTROL REGISTER
TCR          $FFFFB5   ESAI TRANSMIT CONTROL REGISTER
SAICR       $FFFFB4   ESAI COMMON CONTROL REGISTER
SAISR       $FFFFB3   ESAI STATUS REGISTER
                 $FFFFB2   RESERVED
                 $FFFFB1   RESERVED
                 $FFFFB0   RESERVED
                 $FFFFAF   RESERVED
                 $FFFFAE   RESERVED
                 $FFFFAD   RESERVED
                 $FFFFAC   RESERVED
RX3           $FFFFAB   ESAI RECEIVE DATA REGISTER 3
RX2           $FFFFAA   ESAI RECEIVE DATA REGISTER 2
RX1           $FFFFA9   ESAI RECEIVE DATA REGISTER 1
RX0           $FFFFA8   ESAI RECEIVE DATA REGISTER 0
                 $FFFFA7   RESERVED
TSR           $FFFFA6   ESAI TIME SLOT REGISTER
TX5            $FFFFA5   ESAI TRANSMIT DATA REGISTER 5
TX4            $FFFFA4   ESAI TRANSMIT DATA REGISTER 4
TX3            $FFFFA3   ESAI TRANSMIT DATA REGISTER 3
TX2            $FFFFA2   ESAI TRANSMIT DATA REGISTER 2
TX1            $FFFFA1   ESAI TRANSMIT DATA REGISTER 1
TX0            $FFFFA0   ESAI TRANSMIT DATA REGISTER 0
                 $FFFF9F   RESERVED
                 $FFFF9E   RESERVED
                 $FFFF9D   RESERVED
                 $FFFF9C   RESERVED
                 $FFFF9B   RESERVED
                 $FFFF9A   RESERVED
                 $FFFF99   RESERVED
                 $FFFF98   RESERVED
                 $FFFF97   RESERVED
                 $FFFF96   RESERVED
                 $FFFF95   RESERVED

SHI
$FFFF94 SHI RECEIVE FIFO (HRX)
$FFFF93 SHI TRANSMIT REGISTER (HTX)
$FFFF92 SHI I 2 C SLAVE ADDRESS REGISTER (HSAR)
$FFFF91 SHI CONTROL/STATUS REGISTER (HCSR)
$FFFF90 SHI CLOCK CONTROL REGISTER (HCKR)

TRIPLE TIMER
$FFFF8F TIMER 0 CONTROL/STATUS REGISTER (TCSR0)
$FFFF8E TIMER 0 LOAD REGISTER (TLR0)
$FFFF8D TIMER 0 COMPARE REGISTER (TCPR0)
$FFFF8C TIMER 0 COUNT REGISTER (TCR0)
$FFFF8B TIMER 1 CONTROL/STATUS REGISTER (TCSR1)
$FFFF8A TIMER 1 LOAD REGISTER (TLR1)
$FFFF89 TIMER 1 COMPARE REGISTER (TCPR1)
$FFFF88 TIMER 1 COUNT REGISTER (TCR1)
$FFFF87 TIMER 2 CONTROL/STATUS REGISTER (TCSR2)
$FFFF86 TIMER 2 LOAD REGISTER (TLR2)
$FFFF85 TIMER 2 COMPARE REGISTER (TCPR2)
$FFFF84 TIMER 2 COUNT REGISTER (TCR2)
$FFFF83 TIMER PRESCALER LOAD REGISTER (TPLR)
$FFFF82 TIMER PRESCALER COUNT REGISTER (TPCR)
$FFFF81 RESERVED
$FFFF80 RESERVED


Core DCR Channel Priotity Bits
DCR DMA Channel Priotity Bits (18-17) DPR1-DPR0

DMA Control Register DCR

DCR REGISTER, bits 18,17-- The DMA Channel Priority control bits define the priority level of of the DMA channel relative to the othr DMA channels as well as to the priority level of the core when external bus access is required. When DMA transfers are pending, the DMA channel priority level of all the channels are compared to decide which channel will be activated in the next word transfer. This decision must be made since all channels use common resources auch as the DMA address generation logic, the address and data buses etc.
 DPR(1:0) = 00, channel priority level =0(lowest),
 DPR(1:0) = 01, channel priority level = 1,
 DPR(1:0) = 10, channel priority level = 2 and for
 DPR(1:0) = 11 channel priority level =3 (highest) .
 If all or some of the channels  have the same priority, then the channels will be activated  in a round-robin fashion: channel 1 will be activated to transfer one word out of its programmed stream, followed by channel 2 and so on.
If the channel priorities are different, the channel with the highest priority will start executing DMA transfers and will remain doing so as long as there are DMA transfers pending. In the event that a lower priority channel is executing transfers when a higher priority channel receives a transfer request, the lower priority channel will finish the transfer of the current word and arbitration will start again.
If some channels with the same priority are activated in a round-robin fashion and a new channel with higher priority interferes, then after this channel finishes its pending transfers the order of the transfers in the round-robin mode may change, but the algotithm remains ther same.

The DPR (1:0) bits are also used to determine the DMA priority relative to the core priority when an external bus access is required. This function involves the DMA priority level defined by the current active DMA channel, the core priority defined by bits CP(1:0) in Core status register SR and the core-DMA priority defined by bits CDP(1:0) in the core register OMR.

1. When the priority of the DMA is higher than the priority of the core and both require an external access, the DMA will perform the external bus access and the core will wait.

2 When the priority is equal the core will perform all its external accesses pertaining to the current instruction and then the DMA will perform its access.

3. When the priority ot the DMA is lower the core will always perform its external access and the DMA will wait for a free slot in which the  core does not require the external bus.

In the dynamic priority mode (CDP=00), it is possible that a DMA channel will be halted befor e executing both source and destination accesswhen the core has higher priority over the external bus. In this case, if another higher priority DMA channel will request an access, the halted channel will finish its previous access  with the ne  higher priority before the new requesting DMA channel will be serviced.


Core DCR Transfer Mode Bits
DCR Transfer Mode Bits(21-19) DTM2-DTM0

DMA Control Register DCR

DTM(2:0)    Triggered by    DE cleared at end-of-block   Transfer Mode
000            request              yes                                    block transfer
001            request              yes                                    word transfer
010            request              yes                                    line transfer
011            DE                     yes                                    block transfer
100            request               no                                     block transfer
101            request               no                                     word transfer
110            RESERVED
111            RESERVED


DAX Parity Generator PRTYG
DAX Parity Generator

The PRTYG generates the parity bit for the sub-frame being transmitted. The generated parity bit ensures that sub-frame bits four to thirty-one will carry an even number of 1s and 0s.


DMA Registers

Core

DMA Source Address Register DSR
DMA Destination Address Register DDR
DMA Offset Register DOR
DMA Counter Register DCO
DMA Status Register DSTR

DMA Control Register DCR


DSP Side Registers after Reset

R.  Name	R.  Data	HW	SW	IR	ST
HCR	All bits	0	0	----	----
HPCR	All bits	0	0	----	----
HSR	HF1-HF0	0	0	----	----
	HCP	0	0	0	0
	HTDE	1	1	1	1


General Purpose IO
General Purpose I/O

When configured as general-purpose I/O, the HDI08 is viewed by the DSP Core as memory-mapped registers (see Section 2.4) that control up to 16 I/O pins. The software and hardware resets configure HDI08 as general-purpose I/O with all 16 pins  disconnected, by clearing all DSP side control registers (external circuitry connected to these pins may need external pull-up/pull-down resistors until the pins are configured for operation). These registers are the HDI08 port control register (HPCR), the HDI08 data direction register (HDDR), and the HDI08 data register (HDR). Selection between general-purpose I/O and HDI08 is made by clearing HPCR bits 6-1 for  general-purpose I/O or setting these bits for HDI08 functionality. The HDDR configures each corresponding pin in the HDR, as an input pin if the HDDR bit is cleared or as an output pin if the HDDR bit is set (see: HDDR and HDR).


GLOSSARY

A

AGU


HADRB
CSR register HADRB

Paragraph


HCR ModeBits
HCR      HDM2-HDM0 Functionality

HDM2, HDM1, HDM0:
0 0 0      DMA operation disabled
1 0 0      DMA Operation Enabled. Host may set HM1 or HM0 in the ICR to nable
             DMA transfers. (see section TBD)
0 0 1      DMA Mode Data Output Transfers Enabled. (24-Bit words)
0 1 0      DMA Mode Data Output Transfers Enabled. (16-Bit words)
0 1 1      DMA Mode Data Output  Transfers Enabled. (8-Bit words)
1 0 1      DMA Mode Data Input Transfers Enabled. (24-Bit words)
1 1 0      DMA Mode Data Input Transfers Enabled. (16-Bit words)
1 1 1      DMA Mode Data Input Transfers Enabled. (8-Bit words)

ICR Register:    INIT HM1 HBEND HF1 HF0 HDRQ TREQ RREQ

If HDM1 or HDM0 are set, the DMA mode is enabled, and the HREQ pin is used to request DMA transfers (the value of the HM1, HM0, HBEND and HDREQ bits in the ICR have no affect). When the DMA mode is enabled, the HDM2 bit selects the direction of DMA transfers:
 setting HDM2 sets the direction of DMA transfer to be DSP to host and enables the HREQ pin to request data transfer.
 clearing HDM2 sets the direction of DMA transfer to be host to DSP and
enables the HREQ pin to request data transfer.The HACK input pin is used as a DMA transfer acknowledge input. If the DMA direction is from DSP to host, the contents of the selected register are driven onto the host data bus when HACK is asserted. If the DMA direction is from host to DSP, the selected register is written from the host data bus when HACK is asserted.

The size of the DMA word to be transferred is determined by the DMA control bits, HDM0 and HDM1. Only the data registers TXH, TXM, TXL and RXH, RXM, RXL can be accessed in DMA mode.The HDI08 data register selected during a DMA transfer is determined by a 2-bit address counter, which is preloaded with the value in HDM1 and HDM0. The address counter substitutes
for the address bits of the HDI08 during a DMA transfer. The address counter can be initialized with the INIT bit feature. After each DMA transfer on the host data bus, the address counter is incremented to the next register. When the address counter reaches the highest register (RXL or TXL), the address counter is not incremented but is loaded with the value in HDM1 and HDM0. This allows 8-, 16- or 24-bit data to be transferred in a circular fashion and eliminates the need for the DMA controller to supply the HA2, HA1, and HA0 pins. For 16- or 24-bit data transfers, the DSP CPU interrupt rate is reduced by a factor of 2 or 3, respectively, from the host request rate – i.e., for every two or three host processor data transfers of one byte each, there is only one 24-bit DSP CPU interrupt.  The HDM2-HDM0 bits may be changed only if HEN is cleared in the HPCR.


HCTR

Paragraph


HDI08 Host Side Register Map


HNADR

Paragraph


Index

A

AAR

AAR Registers

Acumulator Registers

Address Generation Unit

Address Register

ALC

ALignment Control

Audio Data Register

Audio Data Register Empty

Audio Data Register Empty Interrupt Enable

Audio Data Shift Register

B

BCR

BCR Register

BCR Register

Expansion Port  and DRAM Control

Bit DI

Bit DIR

Bit DO

Bit INV

Bit PCE

Bit TC0-TC3

TCSR register bit  4 to 7

TCSR register bit  4 to 7 tables

Bit TCF

Bit TCIE

Bit TE

Bit TOF

Bit TOIE

Bit TRM

Bit XADE

Bit XAUR

Bit XBIE

Bit XBLK

Bit XCB

Bit XCS

Bit XDIE

Bit XSB

Bit XUA

Bit XUB

Bit XUIE

Bit XVA

Bit XVB

Bits 8 to 9 in ESAI register TCR

Block Transfer Flag

Block Transferred Interrupt Enable Bit

Boundary Scan Register

BSR

C

Channel A Channel Status

Channel A User Data

Channel A Validity

Channel B Channel Status

Channel B User Data

Channel B Validity

Clock Control Register

Clock Input Select

Common Control Register

Contents

Control Register

DAX register XCTR

Topic2

Control/Status Register

Core DCR Channel Priotity Bits

Core DCR Transfer Mode Bits

Counter

CVR

CVR register bit 0 to 6

CVR register bit 7

D

Data ALU

Data Input

Data Output

DAX

DAX  Channel A Channel Status

DAX Audio Data Buffers

DAX Audio Data Register

DAX Audio Data Register Empty

DAX Audio Data Register Empty Interrupt Handling

DAX Audio Data Shift Register

DAX Biphase Encoder

DAX block diagram

DAX Block Transfer Flag

DAX Block Transferred Interrupt Handling

DAX Channel A User Data

DAX Channel A Validity

DAX Channel B Channel Status

DAX Channel B User Data

DAX Channel B Validity

DAX Clock Input Select

DAX Clock Multiplexer

DAX Control Register

DAX Functional Overview

DAX Functional Overview Description

DAX GPIO register PCDR

DAX GPIO register PDRD

DAX GPIO register PRRD

DAX Initiating a Transmit Session

DAX Interrupt Vectors and Priority

DAX Introduction

DAX Non Audio Data Buffer XNADBUF

DAX Non-Audio Data Buffer

DAX Non-Audio Data Register

DAX Operation During Stop

DAX Operation with DMA

DAX Operation with DMA

Table NoAudio Data do not Change from Frame to Frame

Table NonAudio Data Changes from frame to frame

DAX Parity Generator PRTYG

DAX Preamble Generator

DAX Programming Considerations

DAX register XADR

DAX register XADSR

DAX register XCTR

DAX register XNADR

DAX register XSTR

DAX Registers

DAX Registers directly accessible by DSP instructions

DAX Signals

DAX Start Block Bit

DAX Status Register

DAX Transmit Underrun Error Flag

DCO

DCO Register

DCR

Topic2

Topic1

DRAM Control Register DCR

DCR Register

DDR

DDR Register

Destination Address Register

Device Identification Register

IDR Register

Program Control Unit

DI

Digital Audio Transmitter

DIR

Direction

DMA

DMA registers

DMA Status Bit in HSR register

DO

DOR

DOR Register

DR Register

DRAM Control Register

DRAM Control Register DCR

DSP Side Registers after Reset

DSP56362 Registers

DSR

DSR Register

DSTR

DSTR Register

E

ESAI

ESAI Block Diagram

ESAI Clock Generator Functional Block Diagram

ESAI Control and Data Pins

ESAI Generator Block Diagram

ESAI Interrupt Requests

ESAI Introduction

ESAI Operating Modes

ESAI Receive Data Register Full

ESAI Receive Even-Data Register Full

ESAI Receive Odd-Data Register Full

ESAI register RCCR

ESAI register RCR

ESAI Register RSMA and RSMB

ESAI Register SAICR

ESAI Register SAISR

ESAI register TCCR

ESAI register TCR

ESAI register TCR  bit 7

ESAI register TCR bit 0 to 5

ESAI register TCR bit 15

ESAI register TCR bit 16

ESAI register TCR bit 20

ESAI register TCR bit 21

ESAI register TCR bit 22

ESAI register TCR bit 23

ESAI register TCR bit 6

ESAI register TCR bit 7

ESAI register TCR bits 10 to 14

ESAI register TCR bits 8 to 9

ESAI Register TSMA and TSMB

ESAI Registers

ESAI Status Register

ESAI Transmit Clock Control Register

ESAI Transmit Control Register

ESAI Transmit Data Register Empty

ESAI Transmit Even Slot Data Interrupt Enable

ESAI Transmit Even-Data Register Empty

ESAI Transmit Exception Interrupt Enable

ESAI Transmit Interrupt Enable

ESAI Transmit Last Slot Interrupt Enable

ESAI Transmit Odd-Data Register Empty

Expansion Port  and DRAM Control

F

Frame Sync Signal Direction

G

General Purpose IO

Glossary

GPIO (PortD)

GPIO Port C

GPIO Port D

H

HADRB

HBAR

HBEND

HC

HCIE

HCKR

SHI register HCKR

SHI Registers

HCKR register bit 2

HCKR register bits 0 and 1

HCKR register bits 10 to 3

HCKR register bits 13 and 12

HCP

HCR

HCR ModeBits

HCR register bit 0

HCR register bit 1

HCR register bit 2

HCR register bits 3and 4

HCR register bits 5 to 7

HCSR

SHI register HCSR

SHI Registers

HCSR register bit 0

HCSR register bit 1

HCSR register bit 10

HCSR register bit 11

HCSR register bit 14

HCSR register bit 15

HCSR register bit 17

HCSR register bit 19

HCSR register bit 20

HCSR register bit 21

HCSR register bit 22

HCSR register bit 4

HCSR register bit 5

HCSR register bit 6

HCSR register bit 9

HCSR register bits 12 and 13

HCSR register bits 3 to 2

HCSR register bits 8 and 7

HCTR

HDDR

HDI08

HDI08

HDI08 Introduction

HDI08 Block Diagram

HDI08 functionality  of HDR and HDDR

HDI08 Host Side Register Map

HDI08 Introduction

HDI08 register CVR

HDI08 register HBAR

HDI08 register HCR

HDI08 register HDDR and HDR

HDI08 register HORX

HDI08 register HOTX

HDI08 register HPCR

HDI08 register HSR

HDI08 register ICR

HDI08 register ISR

HDI08 register IVR

HDI08 register RXH RXM RXL

HDI08 register TXH TXM TXL

HDM

HDM0 to HDM5 bits in HCR register

HDR

HDRQ bit

HDTE

HEN

HF0

HSR register bits 3 and 4

ICR register bit 3 and 4

HF1

HSR register bits 3 and 4

ICR register bit 3 and 4

ISR register bit 3 and 4

HF2

HCR register bits 3and 4

ISR register bit 3 and 4

HF3

High Frequency Clock Direction

HM0

HM1

HNADR

HORX

Host Command Interrupt Enable

Host Command Pending

Host DMA Mode Control Bits

Host Enable bit in HCSR register

Host Flags

HCR register bits 3and 4

HSR register bits 3 and 4

Host Receive Data Full

Host Receive Interrupt Enable

Host Side Registers After Reset

Host Transmit Data Empty

Host Transmit Interrupt Enable

HOTX

HPCR

HRDF

HREQ

HRIE

HRX

HSAR

SHI register HSAR

SHI Registers

HSR

HSR register  bit 0

HSR register bit 1

HSR register bit 2

HSR register bit 7

HSR register bits 3 and 4

HTIE

HTX

HV

I

I/O Shift Register

I2C Slave Address Register

ICR

ICR register bit 0

ICR register bit 1

ICR register bit 2

ICR register bit 3 and 4

ICR register bit 5

ICR register bit 5 and 6 for HDM 100

ICR register bit 7

ICR register bits for different HDM values

ID

IDR

IDR Register

IF0-IF2

INIT

Input Register

Internal IO Memory Map

Interrupt priority

Interrupt Priority Registers

INV

Inverter Bit

IOSR

SHI register IOSR

SHI Registers

IPR

IPR Interrupt Priority Level Bits

IPR Register

IPR-C

IPR-P

IPRC Register

IPRP Register

ISR

ISR register bit 0

ISR register bit 1

ISR register bit 2

ISR register bit 3 and 4

ISR register bit 7

IVR

J

JTAG

JTAG Boundary Scan Register

JTAG Identification Register

JTAG register BSR

JTAG register ID

L

LA Register

LC Register

Little and Big Endian

Loop Address Register

Loop Count Register

M

Modulo Register

N

Non-Audio Data Buffer

Non-Audio Data Register

O

OBCR Register

OF0-2

Offset REgister

Offset Register

OGDB

OMR

OMR PEN Bit Description

OMR Register

OMR PEN Bit Description

OMR Register

OMR Register

Program Control Unit

OnCE

Operating Mode Register

OSCR Register

OTAGBSR Register

Outline

P

PC Register

PCDR

PCE

PCRC

PCTL Register

PDRC

PLL Clock Oscillator

Port A Address Atribute Registers

Port A Address Attribute Registers

Port A Bus Control Register

Port A Control Register

Port C

Port C Control Registe

Port C Data Register

Port C Direction Register

Port D

Port D Control Register

Port Direction Register

Prescaled Clock Enable

Program Control Unit

Program Counter Register

PRRC

PRRD

PRTYG

R

RCCR

RCCR Frame Sync Signal Direction

RCCR High Frequency Clock Direction

RCCR Receiver Clock Polarity

RCCR Receiver Clock Source Direction

RCCR Receiver Frame Sync Polarity

RCCR Receiver High Frequency Clock Polarity

RCCR register bit 18

RCCR register bit 19

RCCR register bit 20

RCCR register bit 21

RCCR register bit 22

RCCR register bit 23

RCCR register bit 8

RCCR register bits 14 to 17

RCCR register bits 7 to 0

RCCR register bits 9 to 13

RCKD

RCKP

RCR

RCR register bit 15

RCR register bit 16

RCR register bit 20

RCR register bit 21

RCR register bit 22

RCR register bit 23

RCR register bit 6

RCR register bit 7

RCR register bits 10 to 14

RCR register bits 3 to 0

RCR register bits 8 to 9

RDF

Receive Frame Sync Flag

Receiver Clock Polarity

Receiver Clock Source Direction

Receiver Frame Sync Polarity

Receiver High Frequency Clock Polarity

Receiver Overrun Error Flag

REDF

REDIE

REIE

RFS

RFSD

RFSP

RHCKD

RHCKP

RIE

RODF

ROE

RREQ

ICR register bit 0

RREQ

RREQ and TREQ effect

RSWS bits in TCR register

RXDH

RXH

RXL

RXM

S

SAICR

SAICR Alignment Control

SAICR register bit 0 to 2

SAICR register bit 6

SAICR register bit 7

SAICR register bit 8

SAISR

SAISR ESAI Receive Data Register Full

SAISR ESAI Receive Even-Data Register Full

SAISR ESAI Receive Odd-Data Register Full

SAISR ESAI Transmit Data Register Empty

SAISR ESAI Transmit Even-Data Register Empty

SAISR ESAI Transmit Odd-Data Register Empty

SAISR Receive Frame Sync Flag

SAISR Receiver Overrun Error Flag

SAISR register bit  0 to 2

SAISR register bit  6

SAISR register bit  7

SAISR register bit  8

SAISR register bit  9

SAISR register bit 10

SAISR register bit 13

SAISR register bit 14

SAISR register bit 15

SAISR register bit 16

SAISR register bit 17

SAISR Serial Input Flags

SAISR Transmit Frame Sync Flag

SAISR Transmitter Underrun Error Flag

SC Register

Self Chip Select Logic

Serial Audio Interface Module

SHI

SHI  SPI BUS

SHI Block Diagram

SHI Clock Generator

SHI I2C BUS

SHI Internal Architecture

SHI Introduction

SHI Noise Reduction Table

SHI Programming

SHI Receive Interrupt  Enable Bits Table

SHI register HCKR

SHI register HCSR

SHI register HSAR

SHI register IOSR

SHI Registers

SHI Timing Diagram Description

SHI_Timing  Diagram

Source Address Register

SP Register

Program Control Unit

SP Register

SR Register

Program Control Unit

SR Register

Stack Count Register

Stack Extension Pointer

Address Generation Unit

Program Control Unit

Stack Pointer

Stack Size Register

Status Register

DAX register XSTR

Topic2

Program Control Unit

SR Register

Status Register SAISR

SYN

Synchronous Mode Selection

T

Table NoAudio Data do not Change from Frame to Frame

Table NonAudio Data Changes from frame to frame

TC0-TC3

TCSR register bit  4 to 7

TCSR register bit  4 to 7 tables

TCCR

TCCR register bit  7 to 0

TCCR register bit  8

TCCR register bit 13 to 9

TCCR register bit 17 to 14

TCCR register bit 18

TCCR register bit 19

TCCR register bit 20

TCCR register bit 21

TCCR register bit 22

TCCR register bit 23

TCF

TCIE

TCPR

TCR

ESAI register TCR

Triple Timer register TCR

TCSR

TCSR register bit  0

TCSR register bit  1

TCSR register bit  2

TCSR register bit  4 to 7

TCSR register bit  4 to 7 tables

TCSR register bit  8

TCSR register bit  9

TCSR register bit 11

TCSR register bit 12

TCSR register bit 13

TCSR register bit 15

TCSR register bit 20

TCSR register bit 21

TDE

TE

TE5 to TE0 bits in ESAI  TCR register

TEDE

TEDIE

TEIE

TFS

TFSL

TFSR

TIE

Timer  Prescaler Count Register

Timer Compare Flag  Bit

Timer Compare Interrupt Enable

Timer Compare Register

Timer Control Bits

TCSR register bit  4 to 7

TCSR register bit  4 to 7 tables

Timer Control/Status Register

Timer Count Register

Timer Enable

Timer Load Register

Timer Overflow Flag Bit

Timer Overflow Interrupt Enable

Timer Prescaler Register

Timer Register

Triple Timer register TCPR

Triple Timer register TCR

Triple Timer register TCSR

Triple Timer register TLR

Triple Timer register TPCR

Triple Timer register TPLR

Timer reload mode Bit

TLIE

TLR

TMOD

TODE

TOF

TOIE

Topic1

Topic2

TPCR

TPLR

Transmit Frame Sync Flag

Transmit Underrun Error Flag

Transmitter Frame Sync Length

Transmitter Frame Sync Relative Timing

Transmitter Network Mode Contro bits

Transmitter Shift Direction bit

Transmitter Underrun Error Flag

Transmitter Word Alignment Control  bit

TRDY

TREQ bit

Triple Timer Block Diagram

Triple Timer Module

Triple Timer Module Introduction

Triple Timer Module Registers

Triple Timer Operating Modes

Triple Timer register TCPR

Triple Timer register TCR

Triple Timer register TCSR

Triple Timer register TLR

Triple Timer register TPCR

Triple Timer register TPLR

TRM

TSHFD

TSMA

TSMB

TUE

TWA

TXDE

TXH

TXL

TXM

U

Underrun Error Interrupt Enable Bit

V

VBA Register

X

XADBUFA

XADBUFB

XADE

XADR

XADSR

XAUR

XBIE

XBLK

XCA

XCB

XCS[0]

XCS[1]

XCTR

XCTR register bit 0

XCTR register bit 1

XCTR register bit 2

XCTR register bit 3 and 4

XCTR register bit 5

XDIE

XNADBUF

XNADR

XNADR register bit 10

XNADR register bit 11

XNADR register bit 12

XNADR register bit 13

XNADR register bit 14

XNADR register bit 15

XSB

XSTR

XSTR register bit 0

XSTR register bit 1

XSTR register bit 2

XUA

XUB

XUIE

XVA

XVB


OGDB


Outline

 Branch


Outline

 Branch

 Leaf


PCTL Register
PLL Control Register PCTL

Core

Bit 11-0       MF11-MF0   Multiplication Factor Bits
Bit 14-12     DF2-DF0     Division Factor Bits
Bit  15          XTLR            Crystal Range Bit
Bit 16           XTLD            XTAL Disable Bit
Bit 17           PSTP           STOP Processing State Bit
Bit 18           PEN              PLL Enable Bit
Bit 19           COD             Clock Output Disable bit
Bit 23-20     PD3-PD0     PreDivider Factor Bits


RREQ
RREQ Bit 0 in ICR

The RREQ bit is used to control the HREQ and HRREQ pins for host receive data transfers. In interrupt mode (DMA off), RREQ is used to enable host requests via the host request (HREQ or HRRQ) pin when the receive data register full (RXDF) status bit in the ISR is set. If RREQ is cleared, RXDF interrupts are disabled. If RREQ is set, the host request pin (HREQ or HRRQ) will be asserted if RXDF is set.

In DMA modes (HDM2-HDM0 = 100 in the HCR), RREQ must be set or cleared by software to select the direction of DMA transfers. Setting RREQ sets the direction of DMA transfer to be DSP to host and enables the HREQ pin to request data transfer.


SHI Programming


AGU

Address Generation Unit