The Future of Semiconductors: Chips and Chiplets

Dr. Huiming Bu
Vice President, Semiconductor Technology Research & Albany Operation
IBM Research
Mercer Distinguished Lecture Series
DCC 318
Wed, October 12, 2022 at 4:00 PM

We live in a very exciting moment when it comes to the importance of semiconductor chips and technology innovations for the future of computing.
Industry is solutioned at 2nm with GAA Nanosheet transistors. Scaling will continue to 1nm and beyond – driven by the exponential increase in computing need. 3D Vertical Integration is on the horizon and will play a significant role in both chip and chiplet technology in the next decade.
At the device level, the GAA Nanosheet transistor architecture takes advantage of “Z” scaling by stacking multiple nanosheets on top of each other to drive CMOS scaling along with performance improvements. Beyond Nanosheet, it is anticipated that vertical transport transistor or stacked transistors will continue the Z dimensional scaling at the device level.  
At the interconnect level, backside power distribution is a key disruptive innovation that can take advantage of the unused backside of the chip to provide power delivery to devices without consuming front-side wiring realty. This enables continued cell-level scaling and block-level scaling while providing flexibility to independently optimize the chip power distribution for differentiated product requirements.
At the chiplet level, heterogenous integration allows to integrate components as separate dies on a single package. This provides the key benefits of cost as entry point, followed by function optimization and system performance improvements. On top of heterogeneous integration, 3D integration enables coupling high bandwidth memories with accelerators, which make it well-suited for AI compute.

Huiming Bu has 17+ years of professional experience in semiconductor technology R&D at IBM after he received his Ph.D. in Electrical Engineering from Yale University. Huiming started his technical career at IBM on High-/Metal Gate project (32nm/22nm nodes) and then led SOI FinFET research for IBM’s 14nm node technology. After that, Huiming and his team delivered 10nm/7nm R&D for IBM and its joint development partners. In his current role, Huiming is responsible for semiconductor technology roadmap for IBM and partners. He oversees R&D activities in advanced logic (3/2/1nm and beyond), chiplet, emerging memory and analog AI hardware. In addition to driving semiconductor technology R&D agenda, Huiming is also responsible for IBM Research Albany site and fab operation. Huiming has authored/co-authored 100+ technical publications and holds 80+ patents in semiconductor area.