In the post-Moore era, conventional electronic digital computers have become a limiting factor in certain domains, most notably intelligent information processing. The proliferation of big data and artificial intelligence (AI) has motivated the investigation of next-generation AI computing hardware to support massively parallel and energy-hungry machine learning (ML) workloads. Photonic computing, or computing using light, is a disruptive technology that can bring orders-of-magnitude performance and efficiency improvement to AI/ML with its ultra-fast speed, high parallelism, and low energy consumption. There has been growing interest in using nanophotonic processors for performing optical neural network (ONN) inference operations, which can make transformative impacts in future datacenters, automotive, smart sensing, and intelligent edge. However, the substantial potential in photonic computing also brings significant design challenges, which necessitates a cross-layer co-design stack where the circuit, architecture, and algorithm are designed and optimized in synergy. In this talk, I will present my exploration to address the fundamental challenges faced by optical AI and to pioneer a hardware/software co-design methodology toward scalable, reliable, and adaptive photonic neural accelerator designs. First, I will delve into the critical area cost issue of integrated photonic tensor units and present a compact butterfly-style photonic neural chip with domain-specific customization that significantly “compresses” the circuit footprint while realizing comparable inference accuracy. Next, I will present efficient on-chip training frameworks to show how to build a self-learnable photonic accelerator and overcome the robustness and adaptability bottlenecks by directly training the photonic circuits in situ. In particular, the proposed hybrid optimization framework with sparse training techniques can realize unprecedented on-device training scalability and efficiency. In the end, I will conclude the talk with future research directions of developing emerging domain-specific AI hardware with an intelligent end-to-end co-design & automation stack and deploying it to support real-world applications.
Jiaqi Gu is a final-year Ph.D. candidate in the Department of Electrical and Computer Engineering at The University of Texas at Austin, advised by Prof. David Z. Pan and co-advised by Prof. Ray T. Chen. Prior to UT Austin, he received his B.Eng. from Fudan University, Shanghai, China, in 2018. His research interests include emerging post-Moore hardware design for efficient computing, hardware/software co-design, photonic machine learning, and AI/ML algorithms. He has received the Best Paper Award at the ACM/IEEE Asian and South Pacific Design Automation Conference (ASP-DAC) in 2020, the Best Paper Finalist at the ACM/IEEE Design Automation Conference (DAC) in 2020, the Best Poster Award at the NSF Workshop for Machine Learning Hardware Breakthroughs Towards Green AI and Ubiquitous On-Device Intelligence in 2020, the Best Paper Award at the IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (TCAD) in 2021, the ACM Student Research Competition Grand Finals First Place in 2021, and Winner of the Robert S. Hilbert Memorial Optical Design Competition in 2022.