The deployment of Artificial Intelligence (AI) on edge systems has become crucial, given the limited resources of these systems, necessitating cross-layer optimization. Moreover, the unique requirements of edge systems, including security and privacy, have spurred the advancement of AI research. In this presentation, we provide an overview of our efforts to enhance the deployment of AI on edge systems. We begin by introducing efficient AI models using hardware-friendly model compression and topology-aware Neural Architecture Search, thereby optimizing the quality-efficiency trade-off for AI models. Next, we discuss cross-optimization design and efficient distributed learning, which enable the creation of swift and scalable AI systems on specialized hardware. Finally, we demonstrate the improvement in the quality-efficiency trade-off across various applications and scenarios, such as Electronic Design Automation (EDA) and Adversarial Machine Learning. Through these efforts, we present our vision of the future challenges and opportunities associated with full-stack Edge AI.
Yiran Chen received B.S (1998) and M.S. (2001) from Tsinghua University and Ph.D. (2005) from Purdue University. After five years in the industry, he joined the University of Pittsburgh in 2010 as Assistant Professor and was promoted to Associate Professor with tenure in 2014, holding Bicentennial Alumni Faculty Fellow. He is now the John Cocke Distinguished Professor of Electrical and Computer Engineering at Duke University and serving as the director of the NSF AI Institute for Edge Computing Leveraging the Next-generation Networks (Athena), the NSF Industry-University Cooperative Research Center (IUCRC) for Alternative Sustainable and Intelligent Computing (ASIC), and the co-director of Duke Center for Computational Evolutionary Intelligence (DCEI). His group focuses on the research of new memory and storage systems, machine learning and neuromorphic computing, and mobile computing systems. Dr. Chen has published 1 book and more than 500 technical publications and has been granted 96 US patents. He has served as the associate editor of more than a dozen international academic periodicals and served on the technical and organization committees of more than 60 international conferences. He is now serving as the Editor-in-Chief of the IEEE Circuits and Systems Magazine. He received 9 best paper awards, 1 best poster award, and 15 best paper nominations from reputable international conferences and workshops. He received numerous awards for his technical contributions and professional services such as the IEEE Computer Society Edward J. McCluskey Technical Achievement Award, etc. He has been the distinguished lecturer of IEEE CEDA and CAS. He is a Fellow of the ACM, IEEE, and AAAS, and now serves as the chair of ACM SIGDA.