Scaling up quantum processors based on superconducting qubits will require continued technology
improvements in the areas of qubit quality, gate performance, and scalable microwave signal generation and delivery. In recent years at IBM, we have delivered improvements in gate-based superconducting processors that break the 100-qubit barrier, and we have demonstrated coherence time approaching 1 msec on individual qubits. We have demonstrated the capability of solving problems at a scale beyond brute force classical simulation using error mitigation, ushering in the era of quantum utility. Despite these positive developments, fabrication and design challenges need to be overcome to reduce noise and errors further to continue scaling towards the goal of eventual fault-tolerant computation, which requires the capability of running error correction protocols. A key challenge to realize high fidelity quantum circuits, which are the fundamental unit of quantum computation, is coherence stability and reproducibility. This is limited primarily by qubit interactions with two-level systems (TLS) attributed to defects in amorphous materials present at interfaces in the transmission line resonators and Josephson junction (JJ) tunnel barriers. Our hardware development roadmap outlines our plan to extend the utility era by reducing gate errors using a tunable gate architecture that results in faster gates with less crosstalk, improving qubit coherence with TLS mitigation, and increasing qubit count using a modular chip architecture enabled by inter-chip couplers. Finally, increasing qubit connectivity by integrating multi-qubit couplers will enable error correction protocols that can be implemented with a manageable number of qubits.
Dr. Hasan Munir Nayfeh is a senior scientist/engineer at IBM research in Yorktown Heights, New York. His current research focuses on the performance of Quantum computers based on superconducting qubits. Previously at IBM, he researched CMOS transistors for applications down to the 7-nanometer node. Dr. Nayfeh received his B.S. degree in Electrical Engineering from the University of Illinois Urbana-Champaign (UIUC) where he obtained the John Bardeen Award for excellence in undergraduate student research. He went on to achieve his Ph.D. in Electrical Engineering in 2003 from the Massachusetts Institute of Technology (MIT), where he studied the electrostatic and transport properties of nanoscale strained silicon transistors. He has published over 40 papers, granted 9 U.S. patents, and received three IBM Outstanding Technical Achievement Awards: (1) Contributions to scaling up client accessible Quantum computing systems with cutting-edge performance, (2) Two-level system monitoring and mitigation of deployed system, and (3) Contributions to demonstration of utility-scale Quantum computing. He is a Senior member of the IEEE.