Content-Addressable Engines for Associative Processing

A content-addressable parallel processor, or associative processor for short, is a computing and storage architecture from the 1970s based on content-addressable memories, where sequencing bulk search and update memory operations is the primary means to manipulate in situ many operands in parallel, without employing arithmetic circuits. Our research group has been investigating the potential of this computing paradigm in the context of modern microarchitectures, with the goal of providing a processing-in-memory abstraction that is highly data-parallel and programmable. In this talk, I will present some results to date on our Content-Addressable Processing Engine (CAPE), an associative processor architecture that employs CMOS-based push-rule SRAM/CAM logic to carry out data-parallel arithmetic and logic operations, abstracted as very long vector instructions that can be expressed using a RISC-V ISA with standard vector extensions for high programmability. I will describe the basic CAPE architecture and show some promising simulation-based results on a diverse set of data-parallel benchmarks. I will explain how CAPE can be part of a tiled multicore architecture that co-exists and cooperates with CPU cores and on-chip caches. I will also describe our co-design effort in the context of analytical databases.