Over the last fifteen years, hardware security and trust has evolved into a major new area of research at the intersection of semiconductor manufacturing, VLSI design and test, computer-aided design, architecture and system security. During the same period, machine learning has experienced a major revival in interest and has flourished from a nearly forgotten area to the talk of the town. In this presentation, we will first briefly review various machine learning-based solutions which have been developed to address a number of concerns in hardware security and trust, including hardware Trojan detection, counterfeit IC identification, provenance attestation, hardware-based malware detection, side-channel attacks, PUF modeling, etc. Then, we will examine the key attributes of these problems which make them amenable to machine learning-based solutions and we will discuss the potential and the fundamental limitations of such approaches. Lastly, we will ponder the role of and necessity for advanced contemporary machine learning methods in the context of hardware security and we will conclude with suggestions for avoiding common pitfalls when employing such methods.
Yiorgos Makris received the Diploma of Computer Engineering from the University of Patras, Greece, in 1995 and the M.S. and Ph.D. degrees in Computer Engineering from the University of California, San Diego, in 1998 and 2001, respectively. After spending a decade on the faculty of Yale University, he joined UT Dallas where he is now a Professor of Electrical and Computer Engineering, the Co-Founder and Site-PI of the NSF Industry University Cooperative Research Center on Hardware and Embedded System Security and Trust (NSF CHEST I/UCRC), as well as the Leader of the Safety, Security and Healthcare Thrust of the Texas Analog Center of Excellence (TxACE) and the Director of the Trusted and RELiable Architectures (TRELA) Research Laboratory. His research focuses on applications of machine learning and statistical analysis in the development of trusted and reliable integrated circuits and systems, with particular emphasis in the analog/RF domain. He serves as an Associate Editor of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and has served as an Associate Editor for the IEEE Information Forensics and Security and the IEEE Design & Test of Computers Periodical, as a guest editor for the IEEE Transactions on Computers and the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. He also served as the 2016-2017 General Chair and the 2013-2014 Program Chair of the IEEE VLSI Test Symposium. He is a recipient of the 2006 Sheffield Distinguished Teaching Award, Best Paper Awards from the 2013 IEEE/ACM Design Automation and Test in Europe (DATE'13) conference and the 2015 IEEE VLSI Test Symposium (VTS'15), as well as Best Hardware Demonstration Awards from the 2016 and the 2018 IEEE Hardware-Oriented Security and Trust Symposia (HOST'16 and HOST'18) and a recipient of the 2020 Faculty Research