This seminar will review recent advances in doped HfO₂-based ferroelectric devices and their implications for AI hardware design. We will first introduce the fundamentals of ferroelectric field-effect transistors (FeFETs), including the device physics underlying multilevel operation and the impact of process variations. We will then present prototype chip designs fabricated in GlobalFoundries’ 28 nm FeFET technology, demonstrating both analog and digital compute-in-memory (CIM) accelerators for edge AI applications. The talk will subsequently introduce a new concept—non-volatile capacitor (nvCap)—which leverage small-signal, non-destructive read operations rather than the large-signal, destructive read used in conventional ferroelectric random-access memory (FeRAM). The proposed nvCap enables charge-domain computation in capacitive crossbar arrays while consuming only dynamic power. A key engineering objective of nvCap design is to tailor asymmetric C–V characteristics to achieve a large capacitance on/off ratio at zero DC bias. We will first present a metal–ferroelectric–metal (MFM) nvCap as a proof of concept, followed by a FeFET-based metal–ferroelectric–semiconductor (MFS) nvCap that achieves improved capacitance on/off ratio, along with reliability and scaling analysis performed on 300 mm foundry wafers. Finally, we will discuss our ongoing efforts to develop in-house, back-end-of-line (BEOL)-compatible MFS nvCap using oxide semiconductor channel, targeting CMOS+X integration for emerging applications such as capacitive digital compute-in-memory (DCIM), ternary content-addressable memory (TCAM), and inverse matrix solvers.
Shimeng Yu is the endowed Dean’s Professor of Electrical and Computer Engineering at the Georgia Institute of Technology. He received a PhD degree from Stanford University in 2013. He is an elevated IEEE Fellow for contributions to non-volatile memories and in-memory computing. Prof. Yu’s research interests are semiconductor devices and integrated circuits for AI hardware. Among Prof. Yu’s honors, he was a recipient of National Science Foundation (NSF) CAREER Award in 2016, IEEE Electron Devices Society (EDS) Early Career Award in 2017, ACM Special Interests Group on Design Automation (SIGDA) Outstanding New Faculty Award in 2018, Semiconductor Research Corporation (SRC) Inaugural Young Faculty Award in 2019, IEEE Circuits and Systems Society (CASS) Distinguished Lecturer in 2021, IEEE EDS Distinguished Lecturer in 2022, Intel Outstanding Researcher Award in 2023, and SRC Rama Divakaruni Technical Excellence Award in 2025. Prof. Yu’s 500+ journal/conference publications received more than 38,000 citations (Google Scholar) with H-index 86. He is the theme lead of two SRC/DARPA JUMP 2.0 centers on intelligent memory/storage and heterogeneous/monolithic 3D integration. Prof. Yu has served as technical program committee for the leading conferences in the field, including IEEE International Electron Devices Meeting (IEDM), IEEE Symposium on VLSI Technology and Circuits, IEEE International Reliability Physics Symposium (IRPS), ACM/IEEE Design Automation Conference (DAC), ACM/IEEE Design, Automation & Test in Europe (DATE), ACM/IEEE International Conference on Computer-Aided-Design (ICCAD), etc. He also has served as an editor for IEEE Electron Device Letters (EDL), and the associate editor-in-chief for IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS).